PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching

losses and clean, stable operation. Use a multilayer board

whenever possible for better noise immunity and power

dissipation. Follow these guidelines for good PC board

layout:

1) Use a large contiguous copper plane under the

device package. Ensure that all heat-dissipating

components have adequate cooling. The bottom pad

of the devices must be soldered down to this copper

plane for effective heat dissipation and getting the full

power out of the devices. Use multiple vias or a single

large via in this plane for heat dissipation

2) Isolate the power components and high current path

from the sensitive analog circuitry. This is essential to

prevent any noise coupling into the analog signals.

3) Keep the high-current paths short, especially at the

ground terminals. This practice is essential for stable,

jitter-free operation. The high current path compris-

ing of input capacitor, high-side FET, inductor, and the

output capacitor should be as short as possible.

4) Keep the power traces and load connections short.

This practice is essential for high efficiency. Use

thick copper PCBs (2oz vs. 1oz) to enhance full-load

efficiency.

5) The analog signal lines should be routed away from

the high-frequency planes. This ensures integrity of

sensitive signals feeding back into the IC.

6) The ground connection for the analog and power

section should be close to the IC. This keeps the

ground current loops to a minimum. In cases where

only one ground is used, adequate isolation between

analog return signals and high-power signals must be

maintained.

Package Information

For the latest package outline information and land patterns

(footprints), go to

www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

20 TQFN-EP

T2055+4C

21-0140

90-0010

Ordering Information

PART

(FB TIED TO RESISTOR

DIVIDER)

(FB TIED TO BIAS

MAX OPERATING

CURRENT

TEMP TANGE

PIN-PACKAGE

MAX20002ATPA/V+

1V TO 10V

5V

2A

-40°C to +125°C

20 TQFN-EP*

MAX20002ATPB/V+

1V TO 10V

3.3V

2A

-40°C to +125°C

20 TQFN-EP*

MAX20003ATPA/V+

1V TO 10V

5V

3A

-40°C to +125°C

20 TQFN-EP*

MAX20003ATPB/V+

1V TO 10V

3.3V

3A

-40°C to +125°C

20 TQFN-EP*

/V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

*EP = Exposed pad.

www.maximintegrated.com

Maxim Integrated │ 17

MAX20002/MAX20003

36V, 220kHz to 2.2MHz, 2A/3A Fully

Integrated Step-Down Converters

with 15μA Operating Current

Chip Information

PROCESS: BiCMOS