SP813LCP-L datasheet(10/17 Pages) EXAR

10 / 17 page

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Rev. 2.0.0

Fig. 18: SP705/706/813L Watchdog Timing Waveforms

Fig. 19: SP705/706 Timing Diagrams with WDI tri-stated.

POWER-FAIL COMPARATOR

The power-fail comparator can be used for

various purposes because its output and non

inverting input are not internally connected.

The inverting input is internally connected to a

1.25V reference.

To build an early-warning circuit for power

failure, connect the PFI pin to a voltage divider

as shown in Figure 20. Choose the voltage

divider ratio so that the voltage at PFI falls

below 1.25V just before the +5V regulator

drops out. Use PFO to interrupt the µP so it

can prepare for an orderly power-down.

Fig. 20: Typical Operating Circuit

MANUAL RESET

The manual-reset input (MR) allows RESET to

be triggered by a pushbutton switch. The

switch is effectively debounced by the 140ms

minimum RESET pulse width. MR is TTL/CMOS

logic compatible, so it can be driven by an

external logic line. MR can be used to force a

watchdog timeout to generate a RESET pulse

in the SP705/706/813L. Simply connect WDO

to MR.

Ensuring a Valid Reset Output Down to

VCC=0V

When

VCC

falls

below

1.1V,

the

SP705/706/707/708 RESET output no longer

sinks current, it becomes an open circuit.

High-impedance CMOS logic inputs can drift to

undetermined voltages if left undriven. If a

pull-down resistor is added to the RESET pin,

any stray charge or leakage currents will be

shunted to ground, holding RESET LOW. The

resistor value is not critical. It should be about

100KW, large enough not to load RESET and

small enough to pull RESET to ground.

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