3

MB40C328

s PIN DESCRIPTION

The values in parentheses are standard.

s PRECAUTIONS ON USE

Place the high-frequency capacitor as close as possible to the pin.

• To avoid generation of undesired current owing to indetermination of internal logic, set CE to “H” at powering

on and input more than five clock pulses just after operation (CE: “H”

→ “L”).

Pin No.

Symbol

Description

3, 9, 13, 45

Analog power supply (+3.3 V)

16, 27, 43

Digital power supply (+3.3 V)

4, 7, 12, 44

Analog power supply ground pin (0 V)

18, 32, 41

Digital power supply ground pin (0 V)

33 to 40

19 to 26

11

CE

Power down at CE input “H” (internal pull-up resistor)

14

OE

Digital output (Both Port A, B) and clock output (CLKOA, CLKOB) are high

impedance at OE input “H”.

10

CKSEL

Mode of operation setting input pin (Refer to s MODE SETTING)

15

DSEL

28

RESET

Dividing circuit reset input pin (See s TIMING CHART 2, 3)

29

CLK

Clock input pin (max 100 MHz)

31

CLKA

A ch clock input pin (max 50 MHz)

30

CLKB

B ch clock input pin (max 50 MHz)

42

CLKOA

Clock output pin (See s TIMING CHART 1 to 4)

17

CLKOB

Clock output pin (See s TIMING CHART 1 to 4)

Analog input pin

2

1

48

Reference 1/4 voltage output pin (Add 0.1

Reference 1/2 voltage output pin (Add 0.1

Reference 3/4 voltage output pin (Add 0.1

46

Reference voltage input pin on top side

47

Reference voltage output pin

Reference voltage input pin on bottom side

Reference voltage output pin

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