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DV2003S2 датащи(PDF) 2 Page - List of Unclassifed Manufacturers

номер детали DV2003S2
подробное описание детали  Fast Charge Development System Control of On-Board N-FET Switch-Mode Regulator
PDF  6 Pages
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производитель  ETC2 [List of Unclassifed Manufacturers]
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DV2003S2 датащи(HTML) 2 Page - List of Unclassifed Manufacturers

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JP2 TM1
TM1 setting
JP3 TM2
TM2 setting
JP4 NOC
Select number of cells
Fixed Configuration
The DV2003S2 board has the following fixed characteris-
tics :
VCC (4.75–5.25V) is regulated on-board from the supply
at connector JP6 DC+.
LEDs indicate charge status and temperature fault
status.
Pin CCMD is grounded, providing charge initiation on
the later application of the battery or DC+, which pro-
vides VCC to the bq2003.
Pin DCMD is pulled to ground through R12. A toggle of
switch S1 momentarily pulls DCMD high and initiates a
discharge-before-charge. The bq2003 output activates
FET Q4, allowing current to flow through an external
current-limiting load between BAT+ and DSCHG on con-
nector JP6.
Trickle current is limited by a 150
Ω/2W resistor R10 be-
tween DC+ and BAT+ (maximum potential across R10 =
17.3V). Note that too large a voltage between DC+ and
BAT+ may exceed the wattage rating of resistor R10.
As shipped from Benchmarq, the DV2003S1 buck-type
switch-mode regulator is configured to a charging current of
2.35A. This current level is controlled by the value of sense
resistor R26 by the relationship:
I
0.235V
R26
CHG
=
The value of R26 at shipment is 0.100
Ω. This resistor can
be changed depending on the application.
The suggested maximum ICHG for the DV2003S2 board is
3A. A location for a second sense resistor (R27) is pro-
vided on the DV2003S2 board. R27 is electrically in par-
allel with R26, which assists in user modification of ICHG,
if needed.
Charge current can be halted at any time via external
stimulus. Connector JP5 provides a +5V DC source (+V)
and an inhibit input (IN) node for this function. To in-
hibit charge current, the JP5 inhibit input (IN) is driven
by +5V DC.
To re-initiate charge, remove the voltage
source from the inhibit input.
The maximum cell voltage (MCV) setting is 1.8V.
With the provided NTC thermistor connected between
THERM and BAT–, values are: LTF = 10°C, HTF = 45°C,
and TCO = 50°C. The
∆T/∆t settings at 30°C (T∆T) are:
minimum = 0.82°C/minute, typical = 1.10°C/minute.
The thermistor is identified by the serial number suffix
as follows:
Jumper-Selectable Configuration
The DV2003S1 must be configured as described below.
DVEN (JP1): Enables/disables -
∆V termination (see
bq2003 data sheet).
TM1 and TM2 (JP2 and JP3): Select fast charge safety
time/hold-off/top-off (see bq2003 data sheet).
Number of Cells (JP4): A resistor-divider network is
provided to select 2 to 16 cells (the resulting resistor
value equalsN–1 cells). RB1 is a 200K
Ω resistor, and
RB2 (R16–R25) is jumper-selected.
Temperature Disable: Connecting a 10K
Ω resistor be-
tween THERM and BAT– disables temperature control.
2
DV2003S2
Identifier
Thermistor
K1
Keystone RL0703-5744-103-S1
(blank)
Philips 2322-640-63103
F1
Fenwal Type 16, 197-103LA6-A01
O1
Ozhumi 150-108-00(4)
S1
Semetic 103AT-2
Jumper Setting
Pin State
[ 1 2 ] 3
Enabled (high)
1 [ 2 3 ]
Disabled (low)
Jumper Setting
Pin State
[ 1 2 ] 3
High
1 [ 2 3 ]
Low
1 2 3
Float



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