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PM8803TR датащи(PDF) 23 Page - STMicroelectronics

номер детали PM8803TR
подробное описание детали  High-efficiency, IEEE 802.3at compliant integrated PoE-PD interface and PWM controller
PDF  34 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PM8803TR датащи(HTML) 23 Page - STMicroelectronics

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PM8803
PD interface
Doc ID 018559 Rev 2
23/34
This limitation is active after the in-rush phase is completed. The useful programming range
for the current limitation is between 140 mA and 1 A. The practical resistor value range is
between 22 k
Ω and 150 kΩ.
4.6
High-voltage startup regulator
The PM8803 embeds a high-voltage startup regulator to provide a controlled reference
voltage of 8.0 V to the internal current mode PWM controller during its startup phase.
The regulator output is connected to the VC pin as well as to the DC/DC section
In normal isolated topology, the VC pin is diode-connected to the auxiliary winding of the
transformer used for the flyback or forward configuration. When the voltage from the
transformer exceeds the regulated voltage, the high-voltage regulator is shut off, reducing
the amount of power dissipated inside the PM8803.
In more detail, when the voltage from the auxiliary winding exceeds 8.0 V, the regulator
resets its intervention threshold to 7 V. In this way, a loosely regulated voltage from the
auxiliary winding is allowed without current-sharing with the internal regulator.
In the meantime, if the auxiliary voltage fails, the internal regulator takes over without losing
DC/DC control.
The UVLO threshold on VC is 6.0 V typically: at this voltage the DC/DC controller operations
are stopped and the outputs frozen in low state.
While the external auxiliary voltage has to be chosen higher than 8.0 V to take advantage of
the auxiliary winding, it must be also lower than 16 V for all operating conditions, to avoid the
intervention of the internal protection clamp.
A capacitor in the range of 220 nF-10 uF must be connected to DC/DC ground for stability.
For applications with high current drawn from VC, large capacitance should be used (e.g.
10 µF) in order to avoid converter switch-off during the startup phase.
A VC UVLO mechanism monitors the level of voltage on the VC pin. When VC voltage
exceeds the VCUVLO_R, the PWM controller is enabled and it remains enabled until the VC
voltage drops below its VCUVLO_F value.
When an auxiliary winding is not used, the internal HV regulator UVLO threshold is set at
6.6 V and the current limit is set at 20 mA typ. This value includes the current internally
drawn to bias the DC/DC controller, the gate drivers, the VB bias regulator and the external
components that may be connected to the VC and VB pins.
Notice that using the HV regulator without the auxiliary winding increases the internal power
dissipation, and, when operating at high ambient temperature, may lead the device to go
into thermal shutdown.



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