LM5022MM datasheet(13/34 Pages) TI1

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1-D

PC = D x

x RDSON x 1.3

LM5022

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SNVS480E – JANUARY 2007 – REVISED OCTOBER 2011

SWITCHING FREQUENCY

The selection of switching frequency is based on the tradeoffs between size, cost, and efficiency. In general, a

lower frequency means larger, more expensive inductors and capacitors will be needed. A higher switching

frequency generally results in a smaller but less efficient solution, as the power MOSFET gate capacitances must

be charged and discharged more often in a given amount of time. For this application, a frequency of 500 kHz

was selected as a good compromise between the size of the inductor and efficiency. PCB area and component

height are restricted in this application. Following the equation given for RT in the Applications Information

section, a 33.2 k

Ω 1% resistor should be used to switch at 500 kHz.

MOSFET

Selection of the power MOSFET is governed by tradeoffs between cost, size, and efficiency. Breaking down the

losses in the MOSFET is one way to determine relative efficiencies between different devices. For this example,

the SO-8 package provides a balance of a small footprint with good efficiency.

Losses in the MOSFET can be broken down into conduction loss, gate charging loss, and switching loss.

Conduction, or I2R loss, PC, is approximately:

(3)

The factor 1.3 accounts for the increase in MOSFET on resistance due to heating. Alternatively, the factor of 1.3

can be ignored and the maximum on resistance of the MOSFET can be used.

Gate charging loss, PG, results from the current required to charge and discharge the gate capacitance of the

power MOSFET and is approximated as:

PG = VCC x QG x fSW

(4)

QG is the total gate charge of the MOSFET. Gate charge loss differs from conduction and switching losses

because the actual dissipation occurs in the LM5022 and not in the MOSFET itself. If no external bias is applied

to the VCC pin, additional loss in the LM5022 IC occurs as the MOSFET driving current flows through the VCC

regulator. This loss, PVCC, is estimated as:

PVCC = (VIN – VCC) x QG x fSW

(5)

Switching loss, PSW, occurs during the brief transition period as the MOSFET turns on and off. During the

transition period both current and voltage are present in the channel of the MOSFET. The loss can be

approximated as:

PSW = 0.5 x VIN x [IO / (1 – D)] x (tR + tF) x fSW

(6)

Where tR and tF are the rise and fall times of the MOSFET

For this example, the maximum drain-to-source voltage applied across the MOSFET is VO plus the ringing due to

parasitic inductance and capacitance. The maximum drive voltage at the gate of the high side MOSFET is VCC,

or 7V typical. The MOSFET selected must be able to withstand 40V plus any ringing from drain to source, and

be able to handle at least 7V plus ringing from gate to source. A minimum voltage rating of 50VD-S and 10VG-S

MOSFET will be used. Comparing the losses in a spreadsheet leads to a 60VD-S rated MOSFET in SO-8 with an

RDSON of 22 mΩ (the maximum vallue is 31 mΩ), a gate charge of 27 nC, and rise and falls times of 10 ns and

12 ns, respectively.

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