LM48821, LM48821TLEVAL

SNAS354 – JUNE 2007

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Table 4. Volume Control (continued)

VD4

VD3

VD2

VD1

VD0

Gain (dB)

0

1

1

0

0

–14

0

1

1

0

1

–12

0

1

1

1

0

–10

0

1

1

1

1

–8

1

0

0

0

0

–6

1

0

0

0

1

–4

1

0

0

1

0

–2

1

0

0

1

1

0

1

0

1

0

0

2

1

0

1

0

1

4

1

0

1

1

0

6

1

0

1

1

1

8

1

1

0

0

0

10

1

1

0

0

1

12

1

1

0

1

0

13

1

1

0

1

1

14

1

1

1

0

0

15

1

1

1

0

1

16

1

1

1

1

0

17

1

1

1

1

1

18

accomplished with two wires: serial clock (SCL) and serial data (SDA). The clock line is uni-directional. The data

this discussion, the master is the controlling microcontroller and the slave is the LM48821.

Stop Signal.

The start signal is generated by lowering the data signal while the clock signal is high. The start signal will alert

The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.

Each address bit must be stable while the clock level is high.

After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).

Then the master sends an acknowledge clock pulse. If the LM48821 has received the address correctly, then it

holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,

then the master should abort the rest of the data transfer to the LM48821. The 8 bits of data are sent next, most

significant bit first. Each data bit should be valid while the clock level is stable high.

After the data byte is sent, the master must check for another acknowledge to see if the LM48821 received the

data.

If the master has more data bytes to send to the LM48821, then the master can repeat the previous two steps

until all data bytes have been sent.

The stop signal ends the transfer. To signal stop , the data signal goes high while the clock signal is high. The

data line should be held high when not in use.

Table 3. The data values for the volume control are shown in Table 4.

16

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