Bluegiga Technologies Oy

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A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA

memory space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode,

addressing mode, source and destination pointers, and transfer count) is configured with DMA descriptors that

can be located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USARTs,

timers, ADC interface, etc.) can be used with the DMA controller for efficient operation by performing data

transfers between a single SFR or XREG address and flash/SRAM.

Each CC2541 contains a unique 48-bit IEEE address that can be used as the public device address for a

Bluetooth device. Designers are free to use this address, or provide their own, as described in the Bluetooth

specification.

The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which

is associated with one of four interrupt priorities. I/O and sleep timer interrupt requests are serviced even if the

device is in a sleep mode (power modes 1 and 2) by bringing the CC2541 back to the active mode.

The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.

Through this debug interface, it is possible to erase or program the entire flash memory, control which

oscillators are enabled, stop and start execution of the user program, execute instructions on the 8051 core,

set code breakpoints, and single-step through instructions in the code. Using these techniques, it is possible

to perform in-circuit debugging and external flash programming elegantly.

The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral

modules control certain pins or whether they are under software control, and if so, whether each pin is

configured as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral

that connects to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various

applications.

The sleep timer is an ultra-low power timer that uses an external 32.768-kHz crystal oscillator. The sleep timer

runs continuously in all operating modes except power mode 3. Typical applications of this timer are as a real-

time counter or as a wake-up timer to exit power modes 1 or 2.

Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit

period value, and five individually programmable counter/capture channels, each with a 16-bit compare value.

Each of the counter/capture channels can be used as a PWM output or to capture the timing of edges on input

signals. It can also be configured in IR generation mode, where it counts timer 3 periods and the output is

ANDed with the output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.

Timer 2 is a 40-bit timer used by the Bluetooth low energy stack. It has a 16-bit counter with a configurable

timer period and a 24-bit overflow counter that can be used to keep track of the number of periods that have

transpired. A 40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is

received/transmitted or the exact time at which transmission ends. There are two 16-bit timer-compare

registers and two 24-bit overflow-compare registers that can be used to give exact timing for start of RX or TX

to the radio or general interrupts.

Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable

prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of

the counter channels can be used as PWM output.

USART 0 and USART 1 are each configurable as either an SPI master/slave or a UART. They provide double

buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex

applications. Each USART has its own high-precision baud-rate generator, thus leaving the ordinary timers

free for other uses. When configured as SPI slaves, the USARTs sample the input signal using SCK directly

instead of using some oversampling scheme, and are thus well-suited for high data rates.

The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with

128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware

support for CCM.

The ADC supports 7 to 12 bits of resolution with a corresponding range of bandwidths from 30-kHz to 4-kHz,

respectively. DC and audio conversions with up to eight input channels (I/O controller pins) are possible. The

inputs can be selected as single-ended or differential. The reference voltage can be internal, AVDD, or a

single-ended or differential external signal. The ADC also has a temperature-sensor input channel. The ADC

can automate the process of periodic sampling or conversion over a sequence of channels.