AT25DF011 datasheet(3/39 Pages) ETC2

3 / 39 page

AT25DF011

DS-25DF011–032A–4/2014

SO (I/O1)

SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O

1) in conjunction

with other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK.

To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as the

SO pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as

I/O1.

The SO pin will be in a high-impedance state whenever the device is deselected (CS is

deasserted).

Input/

Output

WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer

to “Protection Commands and Features” on page 12 for more details on protection features and

the WP pin.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will

not be used. However, it is recommended that the WP pin also be externally connected to VCC

whenever possible.

Low

Input

HOLD

HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or

resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the

SI pin will be ignored, and the SO pin will be in a high-impedance state.

The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold

condition to start. A Hold condition pauses serial communication only and does not have an

effect on internally self-timed operations such as a program or erase cycle. Please refer to

“Hold” on page 27 for additional details on the Hold operation.

The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be

used. However, it is recommended that the HOLD pin also be externally connected to V

whenever possible.

Low

Input

DEVICE POWER SUPPLY: The V

CC pin is used to supply the source voltage to the device.

Operations at invalid V

CC voltages may produce spurious results and should not be attempted.

Power

GND

GROUND: The ground reference for the power supply. GND should be connected to the system

ground.

Power

Figure 2-1.

8-SOIC Top View

Figure 2-2.

8-TSSOP Top View

Figure 2-3.

8-UDFN (Top View)

Table 2-1.

Pin Descriptions (Continued)

Symbol

Name and Function

Asserted

State

Type

GND

VCC

HOLD

SCK

GND

VCC

HOLD

SCK

GND

VCC

HOLD

SCK

AT25DF011 датащи(PDF) 3 Page - List of Unclassifed Manufacturers

AT25DF011 датащи(HTML) 3 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

датащи скачать

ссылки URL