AD7653 datasheet(20/24 Pages) AD

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AD7625

Data Sheet

Rev. A | Page 20 of 24

Self-Clocked Interface Mode

The digital operation of the AD7625 in self-clocked interface

mode is shown in Figure 30. This interface mode reduces the

number of wires between ADCs and the digital host to two LVDS

pairs per AD7625 (CLK± and D±) or to a single pair if sharing a

common CLK± using multiple AD7625 devices. Self-clocked

interface mode facilitates the design of boards that use multiple

AD7625 devices. The digital host can adapt the interfacing

scheme to account for differing propagation delays between

each AD7625 device and the digital host.

The self-clocked interface mode consists of preceding the results

of each ADC word with a 2-bit header on the data, D±. This

header is used to synchronize D± of each conversion in the

digital host. Synchronization is accomplished by one simple

state machine per AD7625 device. For example, if the state

machine is running at the same speed as CLK± with three

phases, the state machine measures when the Logic 1 of the

header occurs.

Conversions are initiated by a CNV± pulse. The CNV± pulse

must be returned low (≤tCNVH maximum) for valid operation.

After a conversion begins, it continues until completion. Addi-

tional CNV± pulses are ignored during the conversion phase.

After the time tMSB elapses, the host should begin to burst the

CLK±. Note that tMSB is the maximum time for the first bit of

the header and should be used as the gating device for CLK±.

CLK± is also used internally on the host to begin the internal

synchronization state machine. The next header bit and conversion

results are output on subsequent falling edges of CLK±. The

only requirement is that the 18 CLK± pulses finish before the

time tCLKL elapses for the next conversion phase or the data is

lost. Set CLK± to idle high between bursts of 18 CLK± pulses.

CLK+

tCLKL

D+

D–

CLK–

N – 1

ACQUISITION

tCLKD

tCLK

tMSB

D15

D14

D15

N + 1

tCYC

CNV+

tCNVH

SAMPLE N

SAMPLE N + 1

CNV–

tACQ

Figure 30. Self-Clocked Interface Mode Timing Diagram

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