SL28EB742

Preliminary Rev. 0.1

9

2. Functional Description

2.1. Powerdown (PD) Clarification

The CKPWRGD/PD pin is a dual-function pin. During initial powerup, the pin functions as CKPWRGD. Once

CKPWRGD has been sampled high by the clock chip, the pin assumes PD functionality. The PD pin is an

asynchronous active low input used to shut off all clocks cleanly before shutting off power to the device. This signal

is synchronized internally to the device before powering down the clock synthesizer. PD is also an asynchronous

input for powering up the system. When PD is asserted low, clocks are driven to a low value and held before

turning off the VCOs and the crystal oscillator.

2.2. Powerdown (PD) Assertion

When PD is sampled low by two consecutive rising edges of CPUC, all single-ended outputs clocks will be held low

on their next high-to-low transition and differential clocks will be held low. When powerdown mode is desired as the

initial power on state, PD must be asserted low in less than 10 µs after asserting CKPWRGD.

.

Table 6. Output Driver Status during CPU_STP and PCIS_STP

CPU_STP

Asserted

PCI_STP

Asserted

CLKREQ

Asserted

Disabled

Single-ended

Clocks

Stoppable

Running

Driven low

Running

Driven low

Non-stoppable

Running

Running

Running

Differential Clocks

Stoppable

Clock driven high

Clock driven high

Clock driven low

Clock driven low

Clock driven low

Clock driven low

Clock driven low

Non-stoppable

Running

Running

Running

Table 7. Output Driver Status

All Single-ended Clocks

All Differential Clocks

w/o Strap

w/ Strap

Clock

Clock#

PD = 0 (Powerdown)

Low

Hi-z

Low

Low