Product Specification

PE4246

Page 2 of 8

©2003-2010 Peregrine Semiconductor Corp. All rights reserved.

Document No. 70-0090-09

│ UltraCMOS™ RFIC Solutions

Table 2. Pin Descriptions

Table 3. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS™ device, observe the

same precautions that you would use with other ESD-

sensitive devices. Although this device contains

circuitry to protect it from damage due to ESD,

precautions should be taken to avoid exceeding the

rating specified in Table 3.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS™ de-

vices are immune to latch-up.

Table 4. Operating Ranges

Notes: 1. A bypass capacitor should be placed as close as possible

to the pin.

2. Both RF pins must be DC blocked by an external capacitor

3. The exposed pad must be soldered to the ground plane for

proper switch performance.

Figure 3. Pin Configuration

Table 5. Control Logic Truth Table

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be restricted to

the limits in the Operating Ranges table. Operation

between operating range maximum and absolute

maximum for extended periods may reduce reliability.

Pin

No.

Pin

Name

Description

1

2

GND

3

RF1

4

CTRL

CMOS or TTL logic level:

High = RF1 to RF2 signal path

Low = RF1 isolated from RF2

5

GND

6

RF2

Symbol

Parameter/Condition

Min

Max

Unit

Power supply voltage

-0.3

4.0

V

Voltage on CTRL input

-0.3

5.5

V

Storage temperature

-65

150

°C

Input power (50 Ω),

CTRL=1/CTRL=0

33/24

dBm

ESD voltage

(Human Body Model)

200

V

Parameter

Min

Typ

Max

Unit

2.7

3.0

3.3

V

33

40

µA

Control Voltage High

5

V

Control Voltage Low

0

V

-40

85

°C

Control Voltage

Signal Path

CTRL = CMOS or TTL High

RF1 to RF2

CTRL = CMOS or TTL Low

RF1 isolated from RF2

Exposed

Solder Pad

(bottom side)

V

DD

GND

RF1

RF2

GND

CTRL

4

5

6

3

2

1

Device Description

designed to support a variety of applications

where high isolation performance is demanded

and a non-reflective input and output is desired.

This switch is able to replace multiple lesser

performing switches in a very small 3x3 mm DFN

footprint.

Control Logic

The control logic input pin (CTRL) is typically driven by

a 3-volt CMOS logic level signal, and has a threshold of

5-volt control logic drivers, the control logic input has

been designed to handle a 5-volt logic HIGH signal. (A

Moisture Sensitivity Level

The Moisture Sensitivity Level rating for the PE4246 in

the 6-lead 3x3 DFN package is MSL1.

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