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TIMING CHARACTERISTICS

(1) (2)

Input Clock

Analog

Input

Signal

Sample

N

N + 1

N + 2

N + 3

N + 4

N + 1 4

N + 1 6

N + 1 7

N + 1 5

N − 17

N − 16

N − 15

N − 14

N − 13

N − 3

N − 2

N − 1

N

Data Out

(D0−D11)

17.5 Clock Cycles

Data Invalid

Output Clock

ADS5542

SBAS308D – MAY 2004 – REVISED FEBRUARY 2007

Typical values given at T

DRV

otherwise noted

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Switching Specification

Aperture delay

Input CLK falling edge to data sampling point

1

ns

Aperture jitter (uncertainty)

Uncertainty in sampling instant

300

fs

3.2

4.2

ns

Data hold time

1.8

3.0

ns

Input clock rising edge to data valid start delay

3.8

5.0

ns

Input clock to output data valid

8.4

11.0

ns

end

Output clock jitter

Uncertainty in CLKOUT rising edge, peak-to-peak

210

315

Output clock rise time

2.5

2.8

ns

Output clock fall time

2.1

2.3

ns

Input clock to output clock

Input clock rising edge, zero crossing, to output clock rising

7.1

8.0

8.9

ns

delay

edge 50%

Data rise time

5.8

6.6

ns

Data fall time

4.4

5.3

ns

Output enable(OE) to data

Time required for outputs to have stable timings with regard to

1000

Clock

output delay

cycles

Time to valid data after coming out of software power down

1000

Clock

Wakeup time

cycles

Time to valid data after stopping and restarting the clock

1000

Latency

Time for a sample to propagate to the ADC outputs

17.5

Clock

cycles

(1)

Timing parameters are ensured by design and characterization, and not tested in production.

(2)

See Table 5 through Table 6 in the Application Information section for timing information at additional sampling frequencies.

(3)

Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.

(4)

See the Output Information section for details on using the input clock for data capture.

(5)

These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid

number for a falling edge CLKOUT polarity.

(6)

Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect

to input clock.

A.

It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above

timing matches closely with the specified values.

Figure 1. Timing Diagram

6

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