EM73P968 datasheet(32/53 Pages) EMC

32 / 53 page

* This specification are subject to be changed without notice.

8.14.2001

EM73P968

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminar

MSTR: master or slave mode select

0: Master mode

SPI is in master mode and SCK is configured as an output pin.

SPI clock source is internal clock.

1: slave mode

SPI is in slave mode and SCK is configured as an input pin.

SCK receives the serial clock externally.

P18(Bit)

3210

SYMBOL

SPIE

CTR1

CTR0

SPIE: Serial Peripheral Interface Enable

1: Serial Peripheral Interface Enable

0: Serial Peripheral Interface disable

P12, P13 control table

CTR1

CTR0

Select resume

HTC counter

A/D converter

SPI shift data

Unused

SPI control bit:

SPI_F( P14.1): SPI control flag

when SPI register (P12, P13) is empty SPI_F clear 0

when SPI register (P12, P13) is full, SPI_F set 1

P3(Bit)

SYMBOL DCOL

ROM bank select

DCOL (P3.3): SPI control flag

When SPI shift register is empty DCOL clear 0.

When SPI shift register is full DCOL set 1.

SDO: Serial data out ( share with P15.0)

When MSTR set to 0 , SDO is an output pin, share with P15.0,

When the SPI is enable , data are shift out form SDO (P15.0)

SDI: Serial data out (share with P15.0)

When MSTR set to 1 , SDI is an input pin, share with P15.0,

When the SPI is enable , data are shift in form SDI (P15.0)

SCK: Serial Clock (share with P15.1)

The SCK pin for synchronization of both input and output data stream through SDI and SDO pins. When the

MSTR is set, SCK become an output and the Serial clock is supplied to the internal system. When the MSTR

is clear, SCK become an intput and the Serial clock is supplied to the external system. The clock speed in slave

mode is dependent upon the speed of the external system and has a maximum speed up till the internal system

clock.

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