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NG80960JS25 датащи(PDF) 35 Page - Intel Corporation

номер детали NG80960JS25
подробное описание детали  80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
PDF  86 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

NG80960JS25 датащи(HTML) 35 Page - Intel Corporation

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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
Datasheet
35
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
This document contains information on products in the production phase of development. The
specifications within this datasheet are subject to change without prior notice. Verify with your
local Intel sales office or the world wide web to ensure that you have the latest datasheet and device
specification update before finalizing a design.
Warning:
Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These
are stress ratings only. Table 17 presents the absolute maximum ratings.
4.2
Operating Conditions
Warning:
Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond
the “Operating Conditions” may affect device reliability.
Table 18 presents the operating conditions for the 80960Jx 3.3 V processors.
Table 17. Absolute Maximum Ratings
Parameter
Maximum Rating
Storage Temperature
–65o C to +150o C
Case Temperature Under Bias
–65o C to +110o C
Supply Voltage wrt. VSS
–0.5 V to + 4.6 V
Voltage on VCC5 wrt. VSS
–0.5 V to + 6.5 V
Voltage on Other Pins wrt. VSS
–0.5 V to VCC + 0.5 V
Table 18. 80960Jx Operating Conditions
Symbol
Parameter
Min
Max
Units
Notes
VCC
Supply Voltage
3.15
3.45
V
VCC5
Input Protection Bias
3.15
5.5
V
(†)
fCLKIN
Input Clock Frequency
80960JT-100
80960JC-66
80960JC-50
80960JS-33
80960JS-25
80960JD-66
80960JD-50
80960JD-40
80960JD-33
80960JA/JF-33
80960JA/JF-25
80960JA-16
15
15
15
15
15
12
12
12
12
12
12
12
33.3
33.3
25
33
25
33.3
25
20
16.67
33.3
25
16
MHz
TC
Operating Case Temperature
PGA, MPBGA, and PQFP
Extended temp PQFP and MPBGA
0
-40
100
100
°C
†
See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 36.



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