EL4584C

Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these

specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation

4584C

1994 Elantec Inc

Features

 36 MHz general purpose PLL

 Compatible wEL4583 Sync

Separator

 VCXO Xtal or LC tank

oscillator

 User controlled PLL capture and

lock

 Compatible with NTSC and PAL

TV formats

 8 pre-programmed TV scan rate

clock divisors

 Selectable external divide for

custom ratios

 Single 5V low current operation

Applications

 Pixel Clock regeneration

 Video compression engine

(MPEG) clock generator

 Video capture or digitization

 PIP (Picture in Picture) timing

generator

 Text or graphics overlay timing

Ordering Information

Part No

Temp Range Package Outline

EL4584CN -40 Cto a85 C 16-Pin DIP MDP0031

EL4584CS -40 Cto a85 C 16-Lead SO MDP0027

For 6Fsc and 8Fsc clock frequencies

see

EL4585 datasheet

Demo Board

A demo PCB is available for this

product Request ‘‘EL45845 Demo

Board’’

General Description

The EL4584C is a PLL (Phase Lock Loop) sub system designed

for video applications but also suitable for general purpose use

up to 36 MHz In a video application this device generates a

TTLCMOS compatible Pixel Clock (Clk Out) which is a multi-

ple of the TV Horizontal scan rate and phase locked to it

The reference signal is a horizontal sync signal TTLCMOS

format which can be easily derived from an analog composite

video signal with the EL4583 Sync Separator An input signal

to ‘‘coast’’ is provided for applications were periodic distur-

bances are present in the reference video timing such as VTR

head switching The Lock detector output indicates correct lock

The divider ratio is four ratios for NTSC and four similar ratios

for the PAL video timing standards by external selection of

three control pins These four ratios have been selected for com-

(CCIR 601 format) and square picture elements used in some

601 format) etc use the EL4585 which includes an additional

divide by 2 stage

For applications where these frequencies are inappropriate or

for general purpose PLL applications the internal divider can be

bypassed and an external divider chain used

FREQUENCIES and DIVISORS

Function

3Fsc

CCIR 601

Square

4Fsc

Divisor

851

864

944

1135

PAL Fosc (MHz)

13301

135

1475

17734

Divisor

682

858

780

910

NTSC Fosc (MHz)

10738

135

12273

14318

CCIR 601 Divisors yield 720 pixels in the portion of each line for NTSC and PAL

Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL in the active portion

3Fsc numbers do not yield integer divisors

Connection Diagram

EL4584 SO P-DIP Packages

4584 – 17