Compact Flash 5 series

AP-CFxxxxL9XS-XXXXXX

9

© 2012 Apacer Technology Inc.

Rev. 1.2

6. Flash Management

6.1 Intelligent Endurance Design

6.1.1 Advanced wear-leveling algorithms

Flash memory devices differ from Hard Disk Drives (HDDs) in terms of how blocks are utilized. For HDDs,

when a change is made to stored data, like erase or update, the controller mechanism on HDDs will

perform overwrites on blocks. On the other hand, NAND flash storage adopts flash as their primary media.

Unlike HDDs, flash blocks cannot be overwritten and each P/E cycle wears down the lifespan of blocks

gradually. Repeatedly program/erase cycles performed on the same memory cells will eventually cause

some blocks to age faster than others. This would bring flash storages to their end of service term earlier.

Wear leveling is an important mechanism that level out the wearing of blocks so that the wearing-down of

blocks can be almost evenly distributed. This will increase the lifespan of SSDs. Commonly used wear

leveling types are Static and Dynamic.

6.1.2 S.M.A.R.T. Technology

S.M.A.R.T. is an acronym for Self-Monitoring, Analysis and Reporting Technology, an open standard

allowing disk drives to automatically monitor their own health and report potential problems. It protects the

user from unscheduled downtime by monitoring and storing critical drive performance and calibration

parameters. Ideally, this should allow taking proactive actions to prevent impending drive failure. Apacer

SMART feature adopts the standard SMART command B0h to read data from the drive. When the Apacer

SMART Utility running on the host, it analyzes and reports the disk status to the host before the device is

in critical condition.

6.1.3 Built-in Hardware ECC

The ECC bit encoding takes places when host/OS writes data to the SSD. This step is simpler and quick.

On the other hand, the ECC bit decoding is processed when host/OS reads data from the SSD. In this

step, the ECC codes will be in progress for detecting, comparing and detecting potential error. Thus, the

power of the ECC lies mostly in the read data side.

This ATA CompactFlash card employs BCH Error Correction Code (ECC) algorithms. This on-chip

hardware BCH-ECC engines is 13/24 bit programmed that can correct up to 24-bit errors per 1,024 byte

data. This built-in hardware ECC performs parity generation and error detection/correction for data

integrity.

6.2 Intelligent Power Failure Recovery

Power Failure Management ensures data transmission when experiencing unstable power supply. When

power disruption takes places, NAND Flash will have to cache multiple write-to-flash cycles to securely

store data. This urgent operation requires about several milliseconds to get it done. When the supplied

voltage is below a certain percentage of the required, the flash controller will be signaled by a detector IC

component with low power detection signal and then the firmware will communicate the controller to flush

all the data into the cache of Flash storage area. This can prevent incomplete data transmission. The

crucial part lies in the strength of the capacitor of the SSD. The capacitor must be able to hold up some

milliseconds of remaining time before the power is totally out, for the urgent write-back-into-flash

operations to complete.