ZSPM9015

Ultra-Compact, High-Performance, High-Frequency DrMOS Device

Data Sheet

April 26, 2013

© 2013 Zentrum Mikroelektronik Dresden AG

— Rev. 1.00

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the

prior written consent of the copyright owner. The information furnished in this publication is subject to changes without notice.

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5

Circuit Board Layout Considerations

Figure 5.1 provides an example of a proper layout for the ZSPM9015 and critical components. All of the high-

and resistance. This technique achieves a more stable and evenly distributed current flow, along with enhanced

heat radiation and system performance.

The following guidelines are recommendations for the printed circuit board (PCB) designer:

1.

Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-

current power loop inductance and the input current ripple induced by the power MOSFET switching

operation.

2.

DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS

package. The trace should be short and wide enough to present a low-impedance path for the high-

frequency, high-current flow between the DrMOS and inductor to minimize losses and DrMOS temperature

rise. Note that the VSWH node is a high-voltage and high-frequency switching node with a high noise

potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a

heat sink for the lower MOSFET, the designer must balance using the largest area possible to improve

DrMOS cooling with maintaining acceptable noise emission.

3.

Locate the output inductor close to the ZSPM9015 to minimize the power loss due to the VSWH copper trace.

Care should also be taken so that the inductor dissipation does not heat the DrMOS.

4.

The power MOSFETs used in the output stage are effective for minimizing ringing due to fast switching. In

most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and

PGND pins. The resistor and capacitor must be the proper size for the power dissipation.

5.

VCIN and BOOT capacitors should be placed as close as possible the VCIN-to-CGND and BOOT-to-PHASE

pin pairs to ensure clean and stable power. Routing width and length should be considered as well.

6.

operating noise margin in synchronous buck designs that might have noise issues due to ground bounce or

7.

The VIN and PGND pins handle large current transients with frequency components greater than 100MHz. If

possible, these pins should be connected directly to the VIN and board GND planes. Important: the use of

thermal relief traces in series with these pins is discouraged since this adds inductance to the power path.

Added inductance in series with the VIN or PGND pin degrades system noise immunity by increasing positive

8.

Connect the CGND pad and PGND pins to the GND plane copper with multiple vias for stable grounding.

Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead

to faulty operation of the gate driver and MOSFETs.