ZADCS0882/0842/0822

8-Bit, 300ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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List of Figures

Figure 1 Package Pin Assignment for ZADCS0822 & ZADCS0822V........................................................................8

Figure 2 Package Pin Assignment for ZADCS0842 & ZADCS0842V........................................................................9

Figure 3 Package Pin Assignment for ZADCS0822 & ZADCS0822V......................................................................10

Figure 4: Basic application schematic for ZADCS0882V .........................................................................................15

Figure 5: Basic application schematic for ZADCS0882............................................................................................15

Figure 6: Input voltage range in unipolar mode........................................................................................................16

Figure 7: Input voltage range for bipolar mode ........................................................................................................16

Figure 8: Block diagram of input multiplexer ............................................................................................................17

Figure 9: Equivalent input circuit during sampling....................................................................................................17

Figure 10: Reference Adjust Circuit..........................................................................................................................18

Figure 11: 24-Clock External Clock Mode Timing (f

≤ 3.3MHz)

SCLK

.........................................................................19

Figure 12: Internal Clock Mode Timing with interleaved Control Byte transmission ................................................19

Figure 13: 16-Clock External Clock Mode Conversion.............................................................................................20

Figure 14: 11-Clock External Clock Mode Conversion.............................................................................................20

Figure 15 Detailed Timing Diagram..........................................................................................................................21

Figure 16: Unipolar Transfer Function......................................................................................................................22

Figure 17: Bipolar Transfer Function ........................................................................................................................22

Figure 18: Supply Current versus Sampling Rate ....................................................................................................24

Figure 19: Optimal Power-Supply Grounding System..............................................................................................24

Figure 20: Package Outline Dimensions ..................................................................................................................25