DS80C400 datasheet(3/97 Pages) DALLAS

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DS80C400 Network Microcontroller

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most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be

desirable to use a more accurate external reset.

Note 3: While the specifications for VPFW3 and VRST3 overlap, the design of the hardware makes it such that this is not possible. Within the ranges

given, there is a guaranteed separation between these two voltages.

Note 4: Current measured with 75MHz clock source on XTAL1, VCC3 = 3.6V, VCC1 = 2.0V, EA and RST = 0V, Port0 = VCC3, all other pins

disconnected.

Note 5: While the specifications for VPFW1 and VRST1 overlap, the design of the hardware makes it such that this is not possible. Within the ranges

given, there will be a guaranteed separation between these two voltages.

Note 6: Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory

interface function (in parentheses) are as follows: Port 3.6-3.7 (

WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-6.5

(

CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).

Note 7: This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (VOH2). This I/O

pin state can be achieved by applying RST = VCC3.

Note 8: The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot

circuit drives the ports hard for two clock cycles. A weak pullup device (VOH1) remains in effect following the strong two-clock cycle

drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O

mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.

Note 9: Port 3 pins 3.6 (

WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition of

either

WR or RD from a 0 to a 1.

Note 10: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to

1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition

current.

Note 11: Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a

maximum at approximately 2V.

Note 12: During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the Port

0 pin is driven by an external memory source.

Note 13: The OW pin (when configured to output a 1) at VIN = 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],

CRS, COL, MDIO) at VIN = 3.6V.

AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)

(Note 1)

(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.)

75MHz

VARIABLE CLOCK

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

External Crystal Frequency

37.5

Clock Mutliplier 2X Mode

Clock Multiplier 4X Mode

1 / tCLK

18.75

MHz

External Clock Oscillator Frequency

Clock Mutliplier 2X Mode

37.5

Clock Multiplier 4X Mode

1 / tCLK

18.75

MHz

ALE Pulse Width

15.0

tCLCL + tCHCL - 5

Port 0 Instruction Address Valid to ALE Low

tLHLL

1.7

tCHCL - 5

Address Hold After ALE Low

tAVLL

4.7

tCLCH - 2

ALE Low to Valid Instruction In

tLLAX

14.3

2tCLCL + tCLCH - 19

ALE Low to

PSEN Low

tLLIV

3.7

tCLCH - 3

PSEN Pulse Width

tLLPL

21.7

2tCLCL - 5

PSEN Low to Valid Instruction In

tPLPH

9.7

2tCLCL -17

Input Instruction Hold After

PSEN

tPLIV

Input Instruction Float After

PSEN

tPXIX

8.3

tCLCL - 5

Port 0 Address to Valid Instruction In

tAVIV0

21.0

3tCLCL - 19

Port 2, 4, 6 Address or Port 4 CE to Valid

Instruction In

tAVIV2

27.7

3tCLCL + tCLCH - 19

PSEN Low to Address Float

tPLAZ

Note 1: Specifications to -40°C are guaranteed by design and not production tested.

Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.

Note 3: tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external clock (tCLK) as defined in the

External Clock Oscillator (XTAL1) Characteristics table.

Note 4: The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.

Note 5: All signals guaranteed with load capacitance of 80pF except Port 0, Port 2,

ALE, PSEN, RD, and WR with 100pF. The following signals,

when configured for memory interface, are also characterized with 100pF loading: Port 4 (

CE0-3, A16–A19), Port 5.4–5.7 ( PCE0-3),

Port 6.0–6.5 (

CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).

Note 6: For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid bus

contention.

Note 7: References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for

determing absolute signal timing with respect to the external clock.

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