DS1867 datasheet(5/14 Pages) DALLAS

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DS1867

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102199

I/O SHIFT REGISTER Figure 3

17-BIT I/O SHIFT REGISTER

Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper

position value and lastly the potentiometer-0 wiper position value (see Figure 2(a)).

When wiper position data is to be written to the DS1867, 17-bits (or some integer multiple) of data should

always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the

has been completed the RST signal input should be taken to a low state to prevent any inadvertent

changes to the device shift register. Once RST has reached a low state, the contents of the I/O shift

only engage pending a RST transition to the low state. The wiper position for the high-end terminals H0

and H1 will have data values FF (hex), while the low-end terminals will have data values 00 (hex).

STACKED CONFIGURATION

The potentiometers of the DS1867 can be connected in series as shown in Figure 4. This is referred to as

the stacked configuration and allows the user to double the total end-to-end resistance of the part. The

resolution of the combined potentiometers will remain the same as a single potentiometer but with a total

of 512 wiper positions available. Device resolution is defined as RTOT/256 (per potentiometer); where

RTOT is equal to the device resistance value. The wiper output for the combined stacked potentiometer will

be taken at the Sout pin, which is the multiplexed output of the wiper of potentiometer-0 (W0) or

potentiometer-1 (W1). The potentiometer wiper selected at the Sout output is governed by the setting of

the stack select bit (bit-0) of the 17-bit I/O shift register. If the stack select bit has value 0, the multiplexed

output, Sout, will be that of the potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed

output, Sout, will be that of the potentiometer-1 wiper.

STACKED CONFIGURATION Figure 4

CASCADE OPERATION

A feature of the DS1867 is the ability to control multiple devices from a single processor. Multiple

DS1867s can be linked or daisy-chained as shown in Figure 5. As a data bit is entered into the I/O shift

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