DS1644LPM

041697 2/11

CLOCK OPERATIONS –

READING THE CLOCK

While the double buffered register structure reduces the

chance of reading incorrect data, internal updates to the

DS1644L clock registers should be halted before clock

data is read to prevent reading of data in transition.

However, halting the internal clock register updating

process does not affect clock accuracy. Updating is

halted when a one is written into the read bit, the seventh

most significant bit in the control register. As long as a

one remains in that position, updating is halted. After a

halt is issued, the registers reflect the count, that is day,

date, and time that was current at the moment the halt

command was issued. However, the internal clock reg-

isters of the double buffered system continue to update

so that the clock accuracy is not affected by the access

of data. All of the DS1644L registers are updated simul-

taneously after the clock status is reset. Updating is

within a second after the read bit is written to zero.

DS1644L BLOCK DIAGRAM Figure 1

OSCILLATOR AND

CLOCK COUNTDOWN

CHAIN

POWER MONITOR,

SWITCHING, AND

WRITE PROTECTION

POWER GOOD

CLOCK

REGISTERS

CE

WE

A0–A14

DQ0–DQ7

32.768 KHz

+

OE

32K X 8

NV SRAM

PFO