DS1306

6 of 20

The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the

12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is

the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23

hours).

The DS1306 contains two time of day alarms. Time of Day Alarm 0 can be set by writing to registers

87h to 8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. Bit 7 of each of the time

of day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time of day alarm

will only occur once per week when the values stored in timekeeping registers 00h to 03h match the

values stored in the time of day alarm registers. An alarm will be generated every day when bit 7 of the

day alarm register is set to a logic 1. An alarm will be generated every hour when bit 7 of the day and

hour alarm registers is set to a logic 1. Similarly, an alarm will be generated every minute when bit 7 of

the day, hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and

seconds alarm registers is set to a logic 1, an alarm will occur every second.

TIME OF DAY ALARM MASK BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

SECONDS

MINUTES

HOURS

DAYS

1

1

1

1

Alarm once per second

0

1

1

1

Alarm when seconds match

0

0

1

1

Alarm when minutes and seconds match

0

0

0

1

Alarm when hours, minutes, and seconds match

0

0

0

0

Alarm when day, hours, minutes, and seconds

match

SPECIAL PURPOSE REGISTERS

The DS1306 has three additional registers (Control Register, Status Register, and Trickle Charger

Register) that control the real time clock, interrupts, and trickle charger.

CONTROL REGISTER (READ 0FH, WRITE 8FH)

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

0

WP

0

0

0

1 Hz

AIE1

AIE0

WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. When

high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the

control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should

be cleared before attempting to write to the device.

1 Hz (1 Hz output enable) - This bit controls the 1 Hz output. When this bit is a logic 1, the 1 Hz output

is enabled. When this bit is a logic 0, the 1 Hz output is high Z.

AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag

AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag

(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does

not initiate an interrupt signal, and the INT1 pin is set to a logic 0 state.