DS1236 datasheet(2/19 Pages) DALLAS

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DS1236

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input which is debounced and activates reset outputs. An internal watchdog timer can also force the reset

outputs to the active state if the strobe input is not driven low prior to watchdog timeout. Reset control

and wake-up/sleep control inputs also provide the necessary signals for orderly shutdown and startup in

battery backup and battery operated applications. A block diagram of the DS1236 is shown in Figure 1.

PIN DESCRIPTION

PIN NAME

DESCRIPTION

VBAT

+3V battery input provides nonvolatile operation of control functions.

VCCO

VCC output for nonvolatile SRAM applications.

VCC

+5V primary power input.

Power-fail indicator, active high, used for external power switching as shown in

Figure 9.

Power-fail indicator, active low.

WC/ SC

Wake-up and Sleep control. Invokes low-power mode.

Reset control input. Determines reset output. Normally low for NMOS processors and

high for battery backed CMOS processors.

Early warning power-fail input. This voltage sense point can be tied (via resistor

divider) to a user-selected voltage.

NMI

Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending

power failure.

Strobe input. A high-to-low transition will reset the watchdog timer, indicating that

software is still in control.

CEO

Chip enable output. Used with nonvolatile SRAM applications.

CEI

Chip enable input.

PBRST

Pushbutton reset input.

RST

Active low reset output.

RST

Active high reset output.

PROCESSOR MODE

A distinction is often made between CMOS and NMOS processor systems. In a CMOS system, power

consumption may be a concern, and nonvolatile operation is possible by battery backing both the SRAM

and the CMOS processor. All resources would be maintained in the absence of VCC. A power-down reset

is not issued since the low-power mode of most CMOS processors (Stop) is terminated with a Reset. A

pulsed interrupt ( NMI ) is issued to allow the CMOS processor to invoke a sleep mode to save power. For

this case, a power-on reset is desirable to wake up and initialize the processor. The CMOS mode is

invoked by connecting RC to VCCO.

An NMOS processor consumes more power, and consequently may not be battery backed. In this case, it

is desirable to notify the processor of a power-fail, then keep it in reset during the loss of VCC. This avoids

intermittent or aberrant operation. On power-up, the processor will continue to be reset until VCC reaches

an operational level to provide an orderly start. The NMOS mode is invoked by connecting RC to ground.

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