W196
PRELIMINARY
3
Functional Description
I/O Pin Operation
Pins 14 and 27 are dual-purpose l/O pins. Upon power-up
these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of these pins is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-k
Ω “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0”, connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W196 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the REF2X and
24_48MHz clock output buffers are three-stated, allowing the
output strapping resistor on the l/O pin to pull the pin and its
associated capacitive clock load to either a logic HIGH or LOW
state. At the end of the 2-ms period, the established logic “0”
or “1” condition of the l/O pin is then latched. Next the output
buffer is enabled, which converts the l/O pin into an operating
clock output. The 2-ms timer is started when VDD reaches
2.0V. The input bits can only be reset by turning VDD off and
then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock output is 20
Ω (nominal), which is minimally
affected by the 10-k
Ω strap to ground or V
DD. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length to
prevent system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input pe-
riod, a 14.318-MHz output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W196
VDD
Clock Load
10 k
Ω
Output
Buffer
(Load Option 1)
10 k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W196
VDD
Clock Load
R
10 k
Ω
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
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