W161
PRELIMINARY
2
Overview
The W161, a motherboard clock synthesizer, provides 2.5V
CPU clock outputs for advanced CPU and a CPU-divide-by-2
reference frequency for Direct Rambus Clock Generator (such
Cypress W134) interface. Fixed output frequencies are provid-
ed for other system functions.
CPU Frequency Selection
CPU frequency is selected with input pins 25, 29, and 30
(SEL133/100#, SEL0, and SEL1, respectively). Refer to Table
1 for details.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminated clock
lines. The W161 outputs are CMOS-type, which provide
rail-to-rail output swing.
Crystal Oscillator
The W161 requires one input reference clock to synthesize all
output frequencies. The reference clock can be either an ex-
ternally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open.
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W161 incor-
porates the necessary feedback resistor and crystal load ca-
pacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 18 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
18 pF should be used. This will typically yield reference fre-
quency accuracies within ±100 ppm.
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:2
36, 37, 40
O
CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage
swing is controlled by voltage applied to VDDQ2.
PCI0:9
7, 8, 10, 11, 12,
13, 15, 16, 18,
19
O
PCI Clock Outputs 0 through 9: Output voltage swing is controlled by voltage
applied to VDDQ3.
CPUdiv2
43
O
CPU-Divide-By-2 Output: This serves as a reference input signal for Direct
Rambus Clock Generator (Cypress W134). The output voltage is determined
by VDDQ2.
3V66_0:2
21, 22, 23
O
66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by
voltage applied to VDDQ3.
IOAPIC
46
O
I/O APIC Clock Output: Provides an output synchronous to CPU clock. See
Table 1 for their relation to other system clock outputs.
48 MHz
27
O
48-MHz Output: Fixed clock output at 48 MHz.
SPREAD#
31
I
Spread Spectrum Enable: This input enables spread spectrum modulation
on the PLL1 generated frequency outputs of the W161. Modulation range is
–0.5%.
PWRDWN#
32
I
Power Down Control
REF0:1
1, 2
I
Fixed 14.318-MHz Output 0 and 1: Output voltage swing is controlled by
voltage applied to VDDQ3.
SEL0:1
29, 30
I
Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting
clock output modes. As shown in Table 1.
SEL133/100#
25
I
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU
output frequency as shown in Table 1.
X1
4
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
X2
5
I
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
VDDQ2
38, 41, 44, 47
P
Power Connection: Connected to 2.5V power supply.
VDDQ3
3, 9, 17, 24, 28,
34
P
Power Connection: Connected to 3.3V power supply.
GND
6, 14, 20, 26,
33, 35, 39, 42,
45, 48
G
Ground Connection: Connect all ground pins to the common system ground
plane.
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