DTM64360B datasheet(9/13 Pages) ETC2

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DTM64360B

2GB - 240-Pin 1Rx8 Registered ECC DDR3 DIMM

Document 06943, Revision A, 3-Oct-11 Dataram Corporation 



2011

Page 9

Bit 2. CL = 6 -

Bit 3. CL = 7 -

Bit 4. CL = 8 -

Bit 5. CL = 9 -

Bit 6. CL = 10 -

Bit 7. CL = 11 -

CAS Latencies Supported, Most Significant Byte.

Bit 0. CL = 12 -

Bit 1. CL = 13 -

Bit 2. CL =14 -

Bit 3. CL = 15 -

Bit 4. CL = 16 -

Bit 5. CL = 17 -

Bit 6. CL = 18 -

Bit 7. Reserved.

0x00

Minimum CAS Latency Time (tAAmin).

13.125ns

0x69

Minimum Write Recovery Time (tWRmin).

15.0ns

0x78

Minimum RAS# to CAS# Delay Time (tRCDmin).

13.125ns

0x69

Minimum Row Active to Row Active Delay Time (tRRDmin).

6.0ns

0x30

Minimum Row Precharge Delay Time (tRPmin).

13.125ns

0x69

Upper Nibbles for tRAS and tRC.

Bit 3 ~ Bit 0. tRAS Most Significant Nibble -

Bit 7 ~ Bit 4. tRC Most Significant Nibble -

0x11

Minimum Active to Precharge Delay Time (tRASmin), Least

Significant Byte.

36.0ns

0x20

Minimum Active to Active/Refresh Delay Time (tRCmin), Least

Significant Byte.

49.125ns

0x89

Minimum Refresh Recovery Delay Time (tRFCmin), Least

Significant Byte.

160.0ns

0x00

Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant

Byte.

160.0ns

0x05

Minimum Internal Write to Read Command Delay Time (tWTRmin).

7.5ns

0x3C

Minimum Internal Read to Precharge Command Delay Time

(tRTPmin).

7.5ns

0x3C

Upper Nibble for tFAW.

Bit 3 ~ Bit 0. tFAW Most Significant Nibble -

Bit 7 ~ Bit 4. Reserved -

0x00

Minimum Four Activate Window Delay Time (tFAWmin), Least

Significant Byte.

30.0ns

0xF0

SDRAM Optional Features.

Bit 0. RZQ / 6 -

Bit 1. RZQ / 7 -

Bit 6 ~ Bit 2. Reserved -

Bit 7. DLL-Off Mode Support

0x83

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