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CS5101A датащи(PDF) 16 Page - Cirrus Logic |
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CS5101A датащи(HTML) 16 Page - Cirrus Logic |
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16 / 40 page ![]() Output Mode Control The CS5101A and CS5102A can be configured in three different output modes, as well as an in- ternal, synchronous loop-back mode. This allows great flexibility for design into a wide variety of systems. The operating mode is selected by set- ting the states of the SCKMOD and OUTMOD pins. In all modes, data is output on SDATA, starting with the MSB. Each subsequent data bit is updated on the falling edge of SCLK. When SCKMOD is high, SCLK is an input, al- lowing the data to be clocked out with an external serial clock at rates up to 5 MHz. Addi- tional clock edges after #16 will clock out logic ’1’s on SDATA. Tying SCKMOD low reconfig- ures SCLK as an output, and the converter clocks out each bit as it’s determined during the conver- sion process, at a rate of 1/4 the master clock speed. Table 2 shows an overview of the different states of SCKMOD and OUTMOD, and the cor- responding output modes. Pipelined Data Transmission (PDT) PDT mode is selected by tying both SCKMOD and OUTMOD high. In PDT mode, the SCLK pin is an input. Data is registered during conver- sion, and output during the following conversion cycle. HOLD must be brought low, initiating an- other conversion, before data from the previous conversion is available on SDATA. If all the data has not been clocked out before the next falling edge of HOLD, the old data will be lost (Figure 3). Figure 3. Pipelined Data Transmission Mode (PDT) CLKIN (i) HOLD (i) Internal Status SCLK (i) SDATA (o) CH1/2 (i) D15 D14 D1 D0 (Ch. 1) TRK1 (o) TRK2 (o) SSH/SDL (o) Converting Ch. 2 D15 D14 D1 D0 (Ch. 2) Converting Ch. 1 D15 68 72 76 0 4 8 6468 7276 4 8 64 60 60 00 Tracking Ch. 1 Tracking Ch. 2 SCLK Input Output Input Output OUTMOD 0 1 0 1 SCKMOD 0 1 0 1 MODE PDT RBT SSC FRN Input Input Input Output CH1/2 X Input Input Input HOLD Table 2. Serial Output Modes CS5101A CS5102A 16 DS45F2 |
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