CS4954 datasheet(34/56 Pages) CIRRUS

номер детали	CS4954

подробное описание детали	NTSC/PAL Digital Video Encoder

PDF	56 Pages

Scroll/Zoom	100%

производитель	CIRRUS [Cirrus Logic]

домашняя страница	http://www.cirrus.com

Logo

34 / 56 page

CS4954 CS4955

DS278PP4

8.2.

A set of internal registers are available for control-

ling the operation of the CS4954/5. The registers

extend from internal address 0×00 through 0×5A.

Table 9 shows a complete list of these registers and

their internal addresses. Note that this table and the

subsequent register description section describe the

full register map for the CS4954 only. A complete

CS4955 register set description is available only to

Macrovision ACP-PPV Licensed Buyers.

8.2.1. Control Registers

ADDR

PDAT[7:0]

Tas

Twds

Twdh

Twpw

Twr

Twac

Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle

Address

Type

Default value

×00

control_0

r/w

01h

×01

control_1

r/w

02h

×02

control_2

r/w

00h

×03

control_3

r/w

00h

×04

control_4

r/w

3Fh

×05

control_5

r/w

00h

×06

control_6

r/w

00h

×07

RESERVED

×08

bkg_color

r/w

03h

×09

gpio_ctrl_reg

r/w

00h

×0A

gpio_data_reg

r/w

00h

×0B

RESERVED

×0C

RESERVED

×0D

SYNC_0

r/w

90h

×0E

SYNC_1

r/w

F4h

×0F

I2C_ADR

r/w

00h

×10

SC_AMP

r/w

1Ch

×11

SC_SYNTH0

r/w

3Eh

×12

SC_SYNTH1

r/w

F8h

×13

SC_SYNTH2

r/w

E0h

×14

SC_SYNTH3

r/w

43h

×15

HUE_LSB

r/w

00h

×16

HUE_MSB

r/w

00h

Table 9. Control Registers

CS4954 датащи(PDF) 34 Page - Cirrus Logic

CS4954 датащи(HTML) 34 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

датащи скачать

ссылки URL