CS4924 datasheet(52/56 Pages) CIRRUS

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CS4923/4/5/6/7/8/9

DS262F2

AUDATA1—Digital Audio Output 1: Pin 40

PCM multi-format digital-audio data output, capable of two-channel 20-bit output. This PCM

output defaults to DGND as output until enabled by the DSP software. OUTPUT

AUDATA0—Digital Audio Output 0: Pin 41

PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bit

output. This PCM output defaults to DGND as output until enabled by the DSP software.

OUTPUT

MCLK—Audio Master Clock: Pin 44

Bidirectional master audio clock. MCLK can be an output from the CS4923/4/5/6/7/8/9 that

provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be

an input at 128 Fs, 256 Fs, 384 Fs, or 512 Fs. MCLK is used to derive SCLK and LRCLK

when SCLK and LRCLK are driven by the CS492X. BIDIRECTIONAL - Default: INPUT

SCLK—Audio Output Bit Clock: Pin 43

Bidirectional digital-audio output bit clock. SCLK can be an output that is derived from MCLK

to provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs, depending on the MCLK rate and the

digital-output configuration. SCLK can also be an input and must be at least 48Fs or greater.

As an input, SCLK is independent of MCLK. BIDIRECTIONAL - Default: INPUT

LRCLK—Audio Output Sample Rate Clock: Pin 42

Bidirectional digital-audio output-sample-rate clock. LRCLK can be an output that is divided

from MCLK to provide the output sample rate depending on the output configuration. LRCLK

can also be an input. As an input LRCLK is independent of MCLK.

BIDIRECTIONAL - Default: INPUT

XMT958—SPDIF Transmitter Output: Pin 3

CMOS level output that contains a biphase-encoded clock for synchronously providing two

channels of PCM digital audio or a IEC61937 compressed-data interface or both. This output

typically connects to the input of an RS-422 transmitter or to the input of an optical transmitter.

OUTPUT

SCLKN1, STCCLK2—PCM Audio Input Bit Clock: Pin 25

Bidirectional digital-audio bit clock that is an output in master mode and an input in slave

mode. In slave mode, SCLKN1 operates asynchronously from all other CS492X clocks. In

master mode, SCLKN1 is derived from the CS492X internal clock generator. In either master

or slave mode, the active edge of SCLKN1 can be programmed by the DSP. For applications

supporting PES layer synchronization this pin can be used as STCCLK2, which provides a path

to the internal STC 33 bit counter. BIDIRECTIONAL - Default: INPUT

CS4924 датащи(PDF) 52 Page - Cirrus Logic