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CS4812-KM датащи(PDF) 31 Page - Cirrus Logic |
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CS4812-KM датащи(HTML) 31 Page - Cirrus Logic |
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31 / 36 page ![]() CS4812 DS291PP3 31 Serial Control Port SCPM/S - Serial Control Port Master/Slave Select Input: This pin configures the serial control port as a master if tied to VD or a slave if tied to DGND. SPI/I2C - Serial Control Port Format Select Input: This pin configures the control port for I2C format if tied to VD or SPI format if tied to DGND. SCL/CCLK - Serial Control Port Clock Bidirectional: This pin clocks serial control port data into and out of SDA in I2C mode. In SPI mode, it clocks control port data into CDIN and out of CDOUT. When the serial control port is configured as a master, SCL/CCLK is an output and is generated internally. When the serial control port is configured as a slave, SCL/CCLK is an input and may operate asynchronously to the master clock. AD0/CS - I2C Address Bit 0 / SPI Chip Select Bidirectional: In I2C® mode, AD0 is an input and defines bit 0 of the partial chip address. The upper 5 bits of the 7-bit address must be 00100. In SPI mode, CS is the chip select pin. When the serial control port is defined as a master in SPI mode, CS is an output. When the serial control port is defined as a slave in SPI mode, CS is an input. AD1/CDIN - I2C Address Bit 1 / SPI Data Input Input: In I2C® mode, AD1 is an input and defines bit 1 of the partial chip address. The upper 5 bits of the 7-bit address must be 00100. In SPI mode, CDIN is the serial control port data input and is clocked in on the rising edge of CCLK. SDA/CDOUT - I2C Data / SPI Data Output Bidirectional: In I2C® mode, SDA is the bidirectional data I/O line. In SPI mode, CDOUT is the serial control port data output and is clocked out on the falling edge of CCLK. REQ - DSP Output Request Output: This pin is used when the serial control port is configured for slave mode operation. This pin is asserted when the DSP has written a byte to a register in the control port. When this register is read by the master device, REQ is de-asserted. Clock and Crystal XTI, XTO - Crystal Oscillator Connections (Master Clock) Input, Output: These pins provide connections for an external parallel resonant quartz crystal. Alternately, an external clock source may be applied to XTI. The clock frequency must be 256xFs. CLKOUT - Clock Output Output: This pin provides a clock output which can be used to synchronize external components. Available output frequencies 1xFs, 128xFs and 256xFs are selectable via a control port register. The default frequency is 256xFs. It is recommended to externally buffer this signal with a CMOS gate as shown in Figure 5. Miscellaneous PIO0:3 - General Purpose Inputs/Outputs Bidirectional: These pins are general-purpose digital I/O pins. The Default state is input. The functionality of these pins after boot-up is determined by the application firmware code loaded into the device during the boot-up process. RST - Reset Input: This pin causes the device to enter a low power mode and forces all control port and i/o registers to be reset to their default values. The control port can not be accessed when reset is low. |
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