CS4811 datasheet(14/24 Pages) CIRRUS

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CS4811

DS486PP2

3.5

Serial Control Port

The serial control port is used for self-booting from

an external EEPROM and supports both the SPI

bus and the I2C® bus interfaces. The desired inter-

face is selected via the SPI/I2C pin, which is sam-

pled during de-assertion of the RST pin.

3.5.1

SPI Bus

The SPI bus interface consists of 4 digital signals,

CCLK, CDIN, CDOUT and CS. CCLK, the control

port bit clock, is used to clock individual data bits.

CDIN, the control data input, is the serial data input

line to the CS4811. CDOUT, the control data output,

is the output data line from the CS4811. CS, the chip

select signal, is asserted to enable an external SPI

port. Data is clocked in on the rising edge of CCLK

and clocked out on the falling edge.

3.5.1.1

SPI Mode

The SPI master mode is designed for read-only op-

eration during self-booting from a serial EEPROM.

A typical self-boot sequence with a Xicor X25650 se-

rial EEPROM, or equivalent, is shown in Figure 9. On

exit from reset, the CS4811 asserts CS. The 8-bit read

instruction (00000011) is sent to the EEPROM fol-

lowed by a pre-defined 16-bit start address. The

CS4811 then automatically clocks out sequential

bytes from the EEPROM until the last byte has

been received. These bytes include initialization

and configuration data for the device along with the

application firmware code. After the last byte is re-

ceived, the CS4811 deasserts CS and begins program

execution. At this point, the serial control port be-

comes inactive and cannot be accessed.

3.5.2

2C Bus

The I2C bus interface implemented on the CS4811

consists of 2 digital signals, SCL and SDA. SCL or

serial clock, is used to clock individual data bits.

SDA or serial data, is a bidirectional data line. Two

additional pins, AD1 and AD0, are inputs which

determine the 2 lowest order bits of the 7-bit I2C

device address and should be tied to ground.

3.5.2.1

I2C Mode

The I2C master mode is designed for read-only op-

eration during self-booting from a serial EEPROM.

A typical self-boot sequence with a Microchip

X24256 serial EEPROM, or equivalent, is shown

in Figure 10. On exit from reset, the CS4811 sends

an initial write preamble to the EEPROM which

consists of a I2C start condition and the slave ad-

21 22 23 24

CDOUT

READ

COMMAND

16-BIT

ADDRESS = 0X0000

CDIN

DATA

MSB

1 0

0 0 0

1 1

CLK

9 10 11

30 31

25 26 27 28 29

DATA + n

1 0

Figure 9. Control Port Timing, SPI Master Mode Self-Boot

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