CS4341

DS298PP2

3

Analog Output - AOUTA and AOUTB..................................................................................... 22

Reference Ground - REF_GND.............................................................................................. 22

Positive Voltage Reference - FILT+........................................................................................ 22

Quiescent Voltage - VQ ..........................................................................................................22

Master Clock - MCLK .............................................................................................................23

Left/Right Clock - LRCK .........................................................................................................23

Serial Audio Data - SDATA .................................................................................................... 23

Serial Clock - SCLK ................................................................................................................ 24

Reset - RST ............................................................................................................................ 24

Serial Control Interface Clock - SCL/CCLK ........................................................................... 24

Serial Control Data I/O - SDA/CDIN ....................................................................................... 24

Address Bit / Chip Select - AD0/CS........................................................................................ 24

Mute Control - MUTEC ........................................................................................................... 24

6. APPLICATIONS ..................................................................................................................... 25

6.1 Grounding and Power Supply Decoupling ....................................................................... 25

6.2 Oversampling Modes ....................................................................................................... 25

6.3 Recommended Power-up Sequence ............................................................................... 25

6.4 Use of the Power ON/OFF Quiescent Voltage Ramp ..................................................... 25

7. CONTROL PORT INTERFACE .............................................................................................. 26

7.1 SPI Mode ......................................................................................................................... 26

7.2 Memory Address Pointer (MAP) ....................................................................................... 27

8. PARAMETER DEFINITIONS .................................................................................................. 33

Total Harmonic Distortion + Noise (THD+N) .......................................................................... 33

Dynamic Range ...................................................................................................................... 33

Interchannel Isolation ............................................................................................................. 33

Interchannel Gain Mismatch ................................................................................................... 33

Gain Error ............................................................................................................................... 33

Gain Drift ................................................................................................................................ 33

9. REFERENCES ........................................................................................................................ 33

10. PACKAGE DIMENSIONS .................................................................................................... 34

LIST OF FIGURES

Figure 1.

External Serial Mode Input Timing ................................................................................. 9

Figure 2.

Internal Serial Mode Input Timing .................................................................................. 9

Figure 3.

Internal Serial Clock Generation .................................................................................... 9

Figure 4.

I2C Control Port Timing ................................................................................................ 10

Figure 5.

SPI Control Port Timing ...............................................................................................11

Figure 6.

Typical Connection Diagram ........................................................................................ 12

Figure 7.

SPI Mode Control Port Formating ................................................................................ 27

Figure 8.

I2C Mode Control Port Formating ................................................................................ 27

Figure 9.

Base-Rate Stopband Rejection .................................................................................... 28

Figure 10. Base-Rate Transition Band .......................................................................................... 28

Figure 11. Base-Rate Transition Band (Detail) ............................................................................. 28

Figure 12. Base-Rate Passband Ripple ........................................................................................ 28

Figure 13. High-Rate Stopband Rejection .................................................................................... 28

Figure 14. High-Rate Transition Band ........................................................................................... 28

Figure 15. High-Rate Transition Band (Detail) .............................................................................. 29

Figure 16. High-Rate Passband Ripple ......................................................................................... 29

Figure 17. Output Test Load ......................................................................................................... 29