CS4331 datasheet(16/38 Pages) CIRRUS

16 / 38 page

Configuration Register

The CS4330, CS4331, CS4333 support multiple

2’s-complement data/clock formats. The required

format is governed by the contents of the Con-

figuration Register. The 5-bit register determines

which serial data format is acceptable, the fre-

quency of the Internal Serial Clock, on which

edge of SCLK audio data must be valid, and the

number of bits to be loaded into the input buffer.

On initial power-up, the register is loaded with

the default settings, and it is not necessary to

write to the register if this format is appropriate.

The default settings are shown in Figures 4-7.

The 8-bit code includes a 3-bit preamble to pre-

vent accidental access to the Configuration

ing edge of LRCK as shown in the Figures 21

and 22. The code 01000000 is considered to be

an error condition and is ignored. The configura-

tion routine requires that the SDATA pin is held

high, as shown in Figures 21 and 22, to prevent

accidental writing to the register. The Configura-

tion Register is only accessible prior to entering

the External Serial Clock Mode. For I

2S mode,

the user must set B6 to 0, and B7 to 1.

Configuration Access Code

Access Allowed

All other Codes

Access Denied

Internal SCLK Mode only

Sets Internal SCLK/LRCK Ratio *

SCLK/LRCK = 32

Reserved

SCLK/LRCK = 64

SCLK/LRCK = 128

* The Internal SCLK will be 48 Fs, if the

MCLK/LRCK ratio is 384

×.

External SCLK Mode only

Selects Data Sampling edge of SCLK

Rising edge of SCLK

Falling edge of SCLK

Left or Right Justified Data

in relation to LRCK transition

Left Justified

Right Justified

2S Data Format

0Disabled

1Enabled

Sets the number of Bits

18 Bits

16 Bits

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CS4330, CS4331, CS4333

DS136F1

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