CS4297A datasheet(16/52 Pages) CIRRUS

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CS4297A

3.2

AC-Link Audio Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4297A to the AC ’97 con-

troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus-

trates the serial port timing.

The PCM capture data from the CS4297A is shifted out MSB first in the most significant 18 bits of each

slot. The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the

AC ’97 Controller that is less than 18 bits wide, the controller should dither and round or just round (but

not truncate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4297A will always be returned ‘cleared’.

3.2.1

Serial Data Input Slot Tag Bits (Slot 0)

Codec Ready

The Codec Ready bit indicates the readiness of the CS4297A AC-link. Immediately after a

Cold Reset this bit will be ‘clear’. Once the CS4297A clocks and voltages are stable, this bit

will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted

by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref,

or any other analog function. Those must be checked in the Powerdown Control/Status Reg-

ister (Index 26h) by the controller before any access is made to the mixer registers. Any ac-

cesses to the CS4297A while Codec Ready is ‘clear’ are ignored.

Slot 1 Valid

When ‘set’, the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid

When ‘set’, the Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:10] Valid

When ‘set’, the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the

CS4297A ADCs. Only if a Slot [3:10] Valid bit is ‘set’ will the corresponding input slot contain

valid data.

3.2.2

Status Address Port (Slot 1)

RI[6:0]

been requested in the previous frame. The CS4297A will only echo the register index for a

read access. Write accesses will not return valid data in Slot 1.

Bit 15

543210

Codec

Ready

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

00000

Bit 19

3210

RI6

RI5

RI4

RI3

RI2

RI1

RI0

Reserved

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