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CS4224 датащи(PDF) 13 Page - Cirrus Logic |
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CS4224 датащи(HTML) 13 Page - Cirrus Logic |
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13 / 32 page ![]() CS4223 CS4224 DS290PP3 13 5. REGISTER DESCRIPTIONS - CS4224 Note: All registers are read/write in I2C mode and write-only in SPI mode, unless otherwise noted. 5.1 ADC Control (address 01h) 5.1.1 POWER DOWN ADC (PDN) Default = 0 0 - Disabled 1 - Enabled Function: The ADC will enter a low-power state when this function is enabled. 5.1.2 LEFT AND RIGHT CHANNEL HIGH PASS FILTER DEFEAT (HPDR-HPDL) Default = 0 0 - Disabled 1 - Enabled Function: The internal high-pass filter is defeated when this function is enabled. Control of the internal high- pass filter is independent for the left and right channel. 5.1.3 LEFT AND RIGHT CHANNEL ADC MUTING (ADMR-ADML) Default = 0 0 - Disabled 1 - Enabled Function: The output for the selected ADC channel will be muted when this function is enabled. 5.1.4 CALIBRATION CONTROL (CAL) Default = 0 0 - Disabled 1 - Enabled Function: The device will automatically perform an offset calibration when brought out of reset, which last ap- proximately 50 ms. When this function is enabled, a rising edge on the reset line will initiate an offset calibration. 5.1.5 CALIBRATION STATUS (CALP) (READ ONLY) Default = 0 0 - Calibration done 1 - Calibration in progress 765 4321 0 PDN HPDR HPDL ADMR ADML CAL CALP CLKE 000 0000 0 |
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