CS3001

CS3002

10

The loop gainplotshownin Figure 12 illustrates

the unity gain configuration, and indicates how this

is modified when using the amplifier in a higher

gain configuration with compensation. If it is con-

figured for higher gain, for example, 60 dB, the

x–axis will move up by 60 dB (line B). Capacitor

C2 adds a zero and a pole. The modified plot indi-

cates the effects of introducing the pole and zero

due to capacitor C2. The pole can be located at any

frequency higher than the hand-over frequency, the

zero has to be at a frequency lower than the hand-

over frequency so as to provide adequate gain mar-

gin. The separation between the pole and the zero

occurs at the intersection of the –100 dB/decade

and –80 dB/decade slopes. The point X in the fig-

ure should be at closed loop gain plus 20 dB gain

margin.

The value for C2 = 1/(2

πR1p1). Using

p1 = 1 MHz works very well and is independent of

gain. As the closed loop gain is changed, the zero

location is also modified if R1 remains fixed.

Capacitor C2 can be increased in value to limit the

amplifier’s rising noise above 2 kHz.

3.3

Powerdown (

PDWN)

The CS3001 single amplifier provides a power-

down function on pin 1. If this pin is left open the

amplifier will operate normally. If the powerdown

is asserted low, the amplifier will go into a low

power state. There is a pull-up resistor (approxi-

mately 800 k ohm) inside the amplifier from pin

1 to the V+ supply. The current through this pull-up

resistor is the main source of current drain in the

powerdown state.

3.4

Applications

The CS3001 and CS3002 amplifiers are optimum

for applications that require high gain and low drift.

Figure 13 illustrates a thermopile amplifier with a

gain of 650 V/V. The thermopile outputs only a few

millivolts when subjected to infrared radiation. The

amplifier is compensated and bandlimited by C1 in

combination with R2.

-100 dB/dec

-80 dB/dec

z

1

p

1

Margin

-20 dB/dec

50kHz

1MHz

5MHz

Desired Closed

Loop Gain

X

FREQUENCY

B

Figure 12. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation