CS22250 Wireless 10BT Controller

27 of 32

DS551PP2

Rev. 3.0

www.cirrus.com

Table 6. DC Characteristics

Symbol Parameter

Condition

Min

Typ.

Max

Units

Voltage Input Low

-0.50

V

Voltage Input High

V

Voltage Output Low

µA

V

Voltage Output High

µA

V

Input Leakage Current

-10

10

µA

-10

10

µA

Dynamic Supply Current

Note 1

22

123

mA

5.1

AC Characteristics and Timing

Table 7. System Memory Interface Timings

Parameter

Parameter Description

Min

Max

Units

SMCLK to SMD[31:0] output delay

7

ns

SMCLK to SMA[11:0] output delay

4.7

ns

SMCLK to SMDQM[3:0] output delay

5.1

ns

SMCLK to SMNCS[1:0] output delay

4.1

ns

SMCLK to SMNWE output delay

4.5

ns

SMCLK to SMCKE output delay

4.3

ns

SMCLK to SMNCAS output delay

4.0

ns

SMCLK to SMNRAS output delay

5.0

ns

SMCLK period

72

103

ns

SMD[31:0] setup to SMCLK

1.0

ns

SMD[31:0] hold from SMCLK

2.4

ns

Notes:

1.

Outputs are loaded with 35pf on SMD, 25pf on SMA, SMDQM, SMNRAS, and SMNCAS and 20pf

on SMCLK, SMNCS, and SMCKE.

2.

An attempt has been made to balance the setup time needed by the SDRAM and the setup needed

by CS22210 to read data. If there is a problem meeting setup on the SDRAM, there is a

programmable delay line on SMCLK which can help meet the setup time. Care must be taken,

however, not to violate the setup on the return read data. The delay can be increased by a multiple

of 0.25ns by using the SMA[11:09] pins to selectively set the clock delay.