Figure 17 shows the relationship between the regulated

Power-Good from interrupting the CPU unnecessarily, the

pin from toggling Power-Good. The internal time delay is

designed to take about 75µs for Power-Good to go low and

65µs for it to recover. This allows the Power-Good signal to

be completely insensitive to out of regulation conditions

that are present for a duration less than the built in delay

(see Figure 18).

It is therefore required that the output voltage attains an

out of regulation or in regulation level for at least the built-

in delay time duration before the Power-Good signal can

change state.

Figure 18: Power-Good is insensitive to out of regulation conditions that

are present for a duration less than the built in delay.

External Output Enable Circuit

On/off control of the regulator can be implemented

through the addition of two additional discrete compo-

nents (see Figure 19). This circuit operates by pulling the

rent limit condition.

Figure 19: Implementing shutdown with the CS5166H.

Selecting External Components

The CS5166H buck regulator can be used with a wide

range of external power components to optimize the cost

and performance of a particular design. The following

information can be used as general guidelines to assist in

their selection.

NFET Power Transistors

Both logic level and standard FETs can be used. The refer-

ence designs derive gate drive from the 12V supply which

is generally available in most computer systems and utilize

logic level FETs. A charge pump may be easily implement-

ed to permit use of standard FET’s or support 5V or 12V

only systems (maximum of 20V). Multiple FET’s may be

paralleled to reduce losses and improve efficiency and

thermal management.

Voltage applied to the FET gates depends on the applica-

tion circuit used. Both upper and lower gate driver outputs

are specified to drive to within 1.5V of ground when in the

low state and to within 2V of their respective bias supplies

when in the high state. In practice, the FET gates will be

driven rail to rail due to overshoot caused by the capacitive

load they present to the controller IC. For the typical appli-

the regulator output current, the following gate drive is

provided:

(see Figure 20).

Figure 20: Gate drive waveforms depicting rail to rail swing.

Trace 2 = Inductor Switching Node (5V/div.)

Shutdown

Input

5V

CS5166H

SS

5

8

IN4148

MMUN2111T1 (SOT-23)

Trace 1 PWRGD (2V/div)

12

Application Information: continued