Applications Information: continued

10

The bottom FET and board trace must be properly

designed to implement the OVP function.

Figure 12: OVP response to an input-to-output short circuit by immedi-

ately providing 0% duty cycle, crow-barring the input voltage to

ground.

Figure 13: OVP response to an input-to-output short circuit by pulling

the input voltage to ground.

External Output Enable Circuit

On/off control of the regulator can be implemented

through the addition of two additional discrete compo-

nents (see Figure 14). This circuit operates by pulling the

circuit condition.

Figure 14: Implementing shutdown with the CS5155.

External Power Good Circuit

An optional Power Good signal can be generated through

the use of four additional external components (see Figure

15). The threshold voltage of the Power Good signal can be

adjusted per the following equation:

This circuit provides an open collector output that drives

the Power Good output to ground for regulator voltages

Figure 15: Implementing Power Good with the CS5155.

CS5155

R1

10k

R2

6.2k

R3

10k

Power Good

5V

PN3904

PN3904

(R1 + R2)

´ 0.65V

R2

Shutdown

Input

5V

CS5155

SS

5

8

IN4148

MMUN2111T1 (SOT-23)

Trace 4 = 5V from PC Power Supply (2V/div.)

Trace 1 = Regulator Output Voltage (1V/div.)

Trace 4 = 5V from PC Power Supply (5V/div.)

Trace1 = Regulator Output Voltage (1V/div.)

Trace 2 = Inductor Switching Node (5V/div.)