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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5132 датащи(PDF) 2 Page - Cherry Semiconductor Corporation |
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CS5132 датащи(HTML) 2 Page - Cherry Semiconductor Corporation |
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2 / 19 page  2 Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION Absolute Maximum Ratings Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK VCC1 IC Logic and Low Side Driver Power Input 16V -0.3V N/A 1.5A Peak 200mA DC VCC2 IC High Side Drivers Power Input 16V -0.3V N/A 3A Peak 400mA DC COMP1, COMP2 Compensation Pins for the VCORE 6V -0.3V 1mA 5mA and VI/O error amplifiers. VFB1, VOUT1, VID0-4, VCORE Voltage Feedback Input Pin, VOUT2, VFB2, VFFB1, VCORE Output Voltage Sense Pin, VFFB2 Voltage ID DAC Input Pins, VI/O Output Voltage 6V -0.3V 1mA 1mA Sense Pin, VI/O Voltage Feedback Input Pin, VCORE PWM comparator Fast Feedback Pin, VI/O PWM comparator Fast Feedback Pin. COFF1, COFF2 Off-Time Pins for the VCORE and VI/O regulators 6V -0.3V 1mA 50mA GATE(H), GATE High-Side FET Drivers for the VCORE 16V -0.3V 1.5A Peak 1.5A Peak and VI/O regulators. 200mA DC 200mA DC GATE(L) Low-Side FET Driver 16V -0.3V 1.5A Peak 1.5A Peak 200mA DC 200mA DC PWRGD Power-Good Output 6V -0.3V 1mA 30mA OVP Overvoltage Protection 15V -0.3V 30mA 1mA PGnd Power Ground 0V 0V 3A Peak N/A 400mA DC LGnd Logic Ground 0V 0V 40mA N/A 23,24,1,2,3 VIDO Ð VID4 Voltage ID DAC inputs. These pins are internally pulled up to 5.65V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.125V to 3.525V with 100mV incre- ments. When VID4 is low (logic zero), the Error amp reference voltage is 1.325V to 2.075V with 50mV increments. 20 VCC1 Input power supply pin for the internal circuitry, and low side gate driver. Decouple with filter capacitor to PGnd. 17 GATE(H) High side switch FET driver pin for VCORE section. 18 PGnd Power ground for VCORE and VI/O section. 19 GATE(L) Low side synchronous FET driver pin. 16 VCC2 Input power supply pin for on-board high side gate drivers. Decouple with filter capacitor to PGnd. 15 GATE High side switch FET driver pin for VI/O section. 21 OVP Overvoltage protection pin. Goes high when overvoltage condition is detected on VFB1. 22 PWRGD Power-Good Output. Open collector output drives low when VFB1 is out of regulation. Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 125¡C Lead Temperature Soldering: Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sec max. above 183ûC, 230ûC Peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150ûC ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 |
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