7

Application Information: continued

The Line BIAS pin shows a significant change in the regu-

show up as poor line regulation with a low value pull-up

shown in Figure 1.

Clock Synchronization Pin (CS5126 Only)

The CS5126 can be synchronized to signals ranging from

30% slower to several times faster than the internal oscilla-

tor frequency. If the part is synchronized to a fast signal,

maximum duty cycle will be reduced as the frequency

increases as shown in Figure 2.

Figure 2: CS5126 Maximum Duty Cycle vs Frequency (Synchronized

Operation)

If the converter is initially free running and a sync signal is

applied, the current oscillator cycle will terminate and the

oscillator will lock on to the sync signal. The SYNC pin

works with a positive edge triggered signal. When the sync

signal transitions high the current PWM cycle terminates

and a new cycle begins as shown in Figure 3. The typical

phase lag between the rising edge of the SYNC signal and

the rising edge of the Gate is shown in Figure 4. When this

pin is held high or low the internal clock determines the

oscillator frequency.

Figure 3. Synchronized Operation

Figure 4 : Typical Phase Lag between SYNC and GATE on.

Gate Drive

Rail to rail gate driver operation can be obtained (up to

13.5V) over a range of MOSFET input capacitance if the

gate resistor value is kept low. Figure 5 shows the high

driving an IRF220.

8.5

8

7.5

7

6.5

6

0

0.3

0.5

2.5

5

11

Gate Resistor Value

140

130

120

110

100

90

80

70

200kHz

300kHz

400kHz

500kHz

600kHz

SYNC

OSC

GATE

125°C

-40°C

0.82

0.77

0.72

200kHz

300kHz

400kHz

500kHz

600kHz

Frequency

25°C

8.3

8.2

8.1

8

7.9

5µ

10µA20µA50µA

100µA

200µA