AD7656ABSTZ datasheet(17/28 Pages) ETC2

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Data Sheet

AD7656A

Six of the AVCC supply pins are used as the supply to the six ADC

cores on the AD7656A and, as a result, are used for the conversion

process. Each analog input pin is surrounded by an AVCC supply

pin and an AGND pin. These AVCC and AGND pins are the supply

and ground for the individual ADC cores. For example, Pin 33 is

V1, Pin 34 is the AVCC supply for ADC Core 1, and Pin 32 is

AGND for ADC Core 1. An alternative reduced decoupling

solution is to group these six AVCC supply pins into three pairs,

Pin 34 and Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47.

For the AD7656A, a 100 µF decoupling capacitor can be placed

on each of the pin pairs. Decouple all of the other supply and

reference pins with a 10 µF decoupling capacitor.

If the same supply is being used for the AVCC supply and DVCC

supply, place a ferrite or small RC filter between the supply pins.

The AGND pins are connected to the analog ground plane of the

system. The DGND pins are connected to the digital ground plane

in the system. Connect the AGND and DGND planes together

at one place in the system. Make this connection as close as

possible to the AD7656A in the system.

The VDRIVE supply is connected to the same supply as the processor.

The voltage on VDRIVE controls the voltage value of the output

logic signals.

Decouple the VDD and VSS signals with a minimum 10 µF

decoupling capacitor. These supplies are used for the high voltage

analog input structures on the AD7656A analog inputs.

DRIVING THE ANALOG INPUTS

Together, the driver amplifier and the analog input circuit

used for the AD7656A must settle for a full-scale step input to

a 16-bit level (0.0015%), which is within the specified 550 ns

acquisition time of the AD7656A. The noise generated by the

driver amplifier must be kept as low as possible to preserve the

SNR and transition noise performance of the AD7656A. In

addition, the driver needs to have a THD performance suitable

for the AD7656A.

The AD8021 meets all these requirements. The AD8021 needs an

external compensation capacitor of 10 pF. If a dual version of the

AD8021 is required, the AD8022 can be used. The AD8610 and the

AD797 can also be used to drive the AD7656A.

INTERFACE SECTION

The AD7656A provides two interface options: a parallel interface

and a high speed serial interface. The required interface mode is

selected via the SER/PAR SEL pin. The parallel interface can

operate in word (W/B = 0) or byte (W/B = 1) mode. The

interface modes are discussed in the following sections.

Parallel Interface (SER/PAR/SEL = 0)

The AD7656A consists of six 16-bit ADCs. A simultaneous sample

of all six ADCs can be performed by connecting all three CONVST x

pins together (CONVST A, CONVST B, and CONVST C). The

AD7656A needs to see a CONVST x pulse to initiate a conversion;

this typically consists of a falling CONVST x edge followed by a

rising CONVST x edge. The rising edge of CONVST x initiates

simultaneous conversions on the selected ADCs. The AD7656A

contains an on-chip oscillator that is used to perform the

conversions. The conversion time, tCONVERT, is 3 µs. The BUSY signal

goes low to indicate the end of conversion. The falling edge of

the BUSY signal is used to place the track-and-hold amplifier

into track mode. The AD7656A also allows the six ADCs to be

converted simultaneously in pairs by pulsing the three

CONVST x pins independently. CONVST A is used to initiate

simultaneous conversions on V1 and V2, CONVST B is used to

initiate simultaneous conversions on V3 and V4, and CONVST C

is used to initiate simultaneous conversions on V5 and V6. The

conversion results from the simultaneously sampled ADCs are

stored in the output data registers.

Data can be read from the AD7656A via the parallel data bus

with standard CS and RD signals (W/B = 0). To read the data

over the parallel bus, tie SER/PAR SEL low. The CS and RD

input signals are internally gated to enable the conversion result

onto the data bus. The data lines, the DB0 to DB15 pins, leave

their high impedance state when both CS and RD are logic low.

Rev. 0 | Page 17 of 28

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