RL78L1C datasheet(21/153 Pages) RENESAS

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RL78/L1C

2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85 °C)

R01DS0192EJ0200 Rev. 2.00

Page 21 of 149

Feb 21, 2014

2.1

Absolute Maximum Ratings

Note 1.

Connect the REGC pin to VSS via a capacitor (0.47 to 1

F). This value regulates the absolute maximum rating of the

REGC pin. Do not use this pin with voltage applied to it.

Note 2.

Connect the UREGC pin to Vss via a capacitor (0.33

F). This value regulates the absolute maximum rating of the UREGC

pin. Do not use this pin with voltage applied to it.

Note 3.

Must be 6.5 V or lower.

Note 4.

Must be 4.6 V or lower.

Note 5.

Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.

Caution

Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.

That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical

damage, and therefore the product must be used under conditions that ensure that the absolute maximum

ratings are not exceeded.

Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.

Remark 2.

AVREF (+): + side reference voltage of the A/D converter.

Remark 3.

VSS: Reference voltage

Absolute Maximum Ratings (TA = 25

C)

(1/3)

Parameter

Symbols

Conditions

Ratings

Unit

Supply voltage

VDD

-0.5 to + 6.5

UVBUS

-0.5 to + 6.5

AVDD



VDD

-0.5 to + 4.6

REGC pin input voltage

VIREGC

REGC

-0.3 to + 2.8

and -0.3 to VDD + 0.3 Note 1

UREGC pin input voltage

VIUREGC

UREGC

-0.3 to UVBUS + 0.3 Note 2

Input voltage

VI1

P00 to P07, P10 to P17, P20 to P27, P30 to P37,

P40 to P46, P50 to P57, P70 to P77, P80 to P83,

P125 to P127, P137, P140 to P143, EXCLK,

EXCLKS, RESET

-0.3 to VDD + 0.3 Note 3

VI2

P60, P61 (N-ch open-drain)

-0.3 to + 6.5

VI3

UDP, UDM

-0.3 to + 6.5

VI4

P150 to P156

-0.3 to AVDD + 0.3 Note 4

Output voltage

VO1

P00 to P07, P10 to P17, P20 to P27, P30 to P37,

P40 to P46, P50 to P57, P60, P61, P70 to P77,

P80 to P83, P125 to P127, P140 to P143

-0.3 to VDD + 0.3 Note 3

VO2

P130, P150 to P156

-0.3 to AVDD + 0.3 Note 3

VO3

UDP, UDM

-0.3 to + 3.8

Analog input voltage

VAI1

ANI16 to ANI21

-0.3 to VDD + 0.3

and AVREF(+) + 0.3 Notes 3, 5

VAI2

ANI0 to ANI6

-0.3 to AVDD + 0.3

and AVREF(+) + 0.3 Notes 3, 5

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