AD421

–9–

REV. C

The HC11 generates the requisite eight clock pulses with data

valid on the rising edges. After the MSBY is transmitted, the

least significant byte (LSBY) is loaded from memory and

transmitted in a similar fashion. To complete the transfer, the

LATCH pin is driven high when loading the complete 16-bit

word into the AD421.

AD421 TO MICROWIRE INTERFACE

The flexible serial interface of the AD421 is also compatible

with the National Semiconductor MICROWIRE interface. The

MICROWIRE interface is used in microcontrollers such as the

COP400 and COP800 series of processors. A generic interface

to use the MICROWIRE interface is shown in Figure 9. The

G1, SK, and SO pins of the MICROWIRE interface respec-

tively connect to the LATCH, CLOCK, and DATA IN pins of

the AD421.

SK

SO

CLOCK

DATA IN

LATCH

AD421*

MICROWIRE

* ADDITIONAL PINS OMITTED FOR CLARITY

G1

Figure 9. AD421 to MICROWIRE Interface

Opto-Isolated Interface

The AD421 has a versatile serial 3-wire serial interface making

it ideal for minimizing the number of control lines required for

isolation of the digital system from the control loop. In intrinsi-

cally safe applications or due to noise, safety requirements, or

distance, it may be necessary to isolate the AD421 from the

controller. This can easily be achieved by using opto-isolators.

Figure 10 shows an opto-isolated interface to the AD421 where

CLOCK, DATAIN and LATCH are driven from opto-couplers.

Be aware of signal inversion across the opto-couplers. If opto-

couplers with relatively slow rise and fall times are used, Schmitt

triggers may be required on the digital inputs to prevent errone-

ous data being presented to the DAC.

0.1 F

2.2 F

10k

10k

10k

CLOCK

LATCH

DATA IN

AD421*

COM

CLOCK

LATCH

DATA IN

* ADDITIONAL PINS OMITTED FOR CLARITY

Figure 10. Opto-Isolated Interface

APPLICATIONS SECTION

Basic Operating Configuration

Figure 11 shows the basic connection diagram for the AD421

operating at 5 V. This circuit shows the minimum of external

components to operate the AD421. In the diagram, the AD421’s

regulator loop in conjunction with the DN25D pass transistor

pled with a 2.2

µF capacitor to ensure regulator stability and to

the transfer function shifts negative. To correct for this a 16 k

Ω

resistor connected between COM and LOOPRTN will approxi-

5 V to 3 V by adjusting the gain of the AD421.

C1

C2

C3

COM

COM TO EXTERNAL

CIRCUITRY

LV

2.2 F

COM

CIRCUITRY

DN25D

DRIVE

COMP

0.01 F

1k

1000pF

BOOST

LOOP RTN

0.01 F0.01 F

0.0033 F

LATCH

CLOCK

DATA

REF IN

REF OUT2

REF OUT1

4.7 F

COM

AD421

Figure 11. Basic Connection Diagram