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SCF5250LPV100 датащи(PDF) 35 Page - Freescale Semiconductor, Inc |
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SCF5250LPV100 датащи(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 56 page ![]() SCF5250 Data Sheet: Technical Data, Rev. 1.3 Freescale Semiconductor 35 Figure 12 provides the SCLK input, SDATA output timing diagram for the IIS module and Table 31 provides the timing parameters. Figure 12. SCLK Input, SDATA Output Timing Diagram Figure 13 provides the SCLK output, SDATA output timing diagram for the IIS module and Table 32 provides the timing parameters. Figure 13. SCLK Output, SDATA Output Timing Diagram J11 TCK falling to Boundary Scan Data Valid (signal from driven or three-state) – tbd ns J12 TCK falling to Boundary Scan. Data High Impedance – tbd ns Table 31. SCLK Input, SDATA Output Timing Specifications Num Characteristic Min Max Units TU SCLK fall to SDATAO rise – 25 ns TD SCLK fall to SDATAO fall – 25 ns Table 32. SCLK Output, SDATA Output Timing Specifications Num Characteristic Min Max Units TU SCLK fall to SDATAO rise – 3 ns TD SCLK fall to SDATAO fall – 3 ns Table 30. JTAG AC Timing Specifications (continued) Num Characteristic Min Max Units SCLK (INPUT) SDATAO1, 2 (OUTPUT) TU TD SCLK (OUTPUT) SDATAO1, 2 (OUTPUT) TU TD |
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