5-79

FAST AND LS TTL DATA

DUAL JK FLIP-FLOP

WITH SET AND CLEAR

The SN54/ 74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-

rect Clear inputs. These dual flip-flops are designed so that when the clock

goes HIGH, the inputs are enabled and data will be accepted. The Logic Level

of the J and K inputs will perform according to the Truth Table as long as mini-

mum set-up times are observed. Input data is transferred to the outputs on the

HIGH-to-LOW clock transitions.

MODE SELECT — TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

OPERATING MODE

SD

CD

J

K

Q

Q

Set

Reset (Clear)

*Undetermined

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

L

H

L

H

H

H

H

H

L

L

H

H

H

H

X

X

X

h

l

h

l

X

X

X

h

h

l

l

H

L

H

q

L

H

q

L

H

H

q

H

L

q

*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable

if SD and CD go HIGH simultaneously.

H,h = HIGH Voltage Level

L,l = LOW Voltage Level

X = Immaterial

l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior

to the HIGH-to-LOW clock transition

LOGIC DIAGRAM

Q

CLEAR (CD)

J

CLOCK (CP)

K

SET (SD)

Q

SN54/74LS76A

DUAL JK FLIP-FLOP

WITH SET AND CLEAR

LOW POWER SCHOTTKY

LOGIC SYMBOL

16

1

4

15

14

K

Q

CP

J

Q

SD

VCC = PIN 5

GND = PIN 13

12

6

9

11

10

K

Q

CP

J

Q

CD

7

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXJ

Ceramic

SN74LSXXN

Plastic

SN74LSXXD

SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

2

3

8

CD

SD