AS3430 datasheet(31/51 Pages) AMSCO

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AS3400 AS3410 AS3430 1v0

Data Sheet - R e g i s t e r D e s c r i p t i o n

Table 19. GP_OP_R Register

Name

Base

Default

GP_OP_R

2-wire serial

00h

Offset: 0Ch

Right General Purpose Operational Amplifier Register

Enables the right opamp stages, defines opamp 2 mode and gain and sets the HP mode. This register is

reset at POR.

Bit

Bit Name

Default

Access

Bit Description

OP_REG_ON

R/W

Defines which register is used for the opamp and HP settings.

0: settings of register 33h and 34h are used

1: register 0B and 0Ch are used

HP_MODE

R/W

Selects the line input mode

0: single ended stereo mode

1: mono differential mode

5:2

OP2R<3:0>

0000

R/W

Mode and volume settings for right OP2, adjustable in 15 steps of 0.75dB

0000: OP2R in inverting mode

0001: 0 dB gain, OP2R in non inverting mode

0001: 0.75 dB gain, non inverting

..,

1110: 9.75dB gain, non inverting

1111:.10.5 dB gain, non inverting

OP2R_ON

R/W

Enables right OP 2

0: right OP2 is switched off

1: right OP2 is enabled

OP1R_ON

R/W

Enables right OP 1

0: right OP1 is switched off

1: right OP1 is enabled

Table 20. SYSTEM Register

Name

Base

Default

SYSTEM

2-wire serial

31h

Offset: 20h

SYSTEM Register

This register is reset at a POR.

Bit

Bit Name

Default

Access

Bit Description

7:4

Design_Version<3:0>

0100

AFE number to identify the design version

0100: for chip version 1v0

TESTREG_ON

R/W

0: normal operation

1: enables writing to test register 3Eh & 3Fh to configure the OTP and set

the access mode.

MONITOR_ON

R/W

Enables the monitor mode

0: normal operation

1: monitor mode enabled

CONT_PWRUP

R/W

Continues the automatic power-up sequence when using the I2C mode

0: chip stops the power-up sequence after the supplies are stable,

switching on individual blocks has to be done via I2C commands

1: automatic power-up sequence is continued

PWR_HOLD

R/W

0: power up hold is cleared and AFE will power down

1: is automatically set to on after power on

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