ADM8323/ADM8324

Data Sheet

Rev. 0 | Page 10 of 16

THEORY OF OPERATION

CIRCUIT DESCRIPTION

The ADM8323/ADM8324 provide microprocessor supply

voltage supervision by controlling the microprocessor reset input.

Code execution errors are avoided during power-up, power-

down, and brownout conditions by asserting a reset signal when

the supply voltage is below a preset threshold and by allowing

supply voltage stabilization with a fixed timeout reset pulse

after the supply voltage rises above the threshold. In addition,

problems with microprocessor code execution can be monitored

and corrected with a windowed watchdog timer. If the user

detects a problem with system operation, a manual reset input is

available to reset the microprocessor, for example, by means of

an external push-button switch.

PUSH-PULL RESET OUTPUT

The ADM8323 features an active low push-pull reset output.

within the watchdog timeout window. Reset remains asserted for

rises above the reset threshold, after MR transitions from low to

high, or after the watchdog timer fault occurs. Figure 20

illustrates the behavior of the reset output.

Figure 20. Reset Timing Diagram

OPEN-DRAIN RESET OUTPUT

The ADM8324 has an active low, open-drain reset output. This

output structure requires an external pull-up resistor to connect

the reset output to a voltage rail no higher than Vcc. Use a

resistor that complies with the logic low and logic high voltage

level requirements of the microprocessor while supplying input

current and leakage paths on the RESET line. A 10 kΩ resistor

is adequate in most situations.

MANUAL RESET INPUT

The ADM8323/ADM8324 feature a manual reset input (MR),

which when driven low, asserts the reset output. When MR

transitions from low to high, the reset output remains asserted

for the duration of the reset active timeout period before

deasserting. The MR input has a 75 kΩ, internal pull-up resistor

so that the input is always high when unconnected. An external

push-button switch can be connected between MR and ground

so that the user can generate a reset. Debounce circuitry for this

purpose is integrated on chip. Noise immunity is provided on

the MR input, and fast, negative going transients of up to 100 ns

(typical) are ignored. A 0.1 µF capacitor between MR and ground

provides additional noise immunity.

WINDOWED WATCHDOG INPUT

The ADM8323/ADM8324 feature a windowed watchdog timer

that monitors microprocessor activity. A timer circuit is cleared

with every high-to-low logic transition on the watchdog input pin

(WDI), which detects pulses as short as 200 ns. If this watchdog

pulse does not occur within the defined time window, a reset

asserts. Failure of the microprocessor to toggle WDI within the

watchdog window, therefore, indicates a code execution error,

and the reset pulse generated restarts the microprocessor in a

known state.

As well as logic transitions on WDI, the watchdog timer is also

cleared by a reset assertion due to an undervoltage condition on

watchdog timer is cleared and does not begin counting again

until the reset deassserts. The windowed watchdog timer cannot

be disabled.

All WDI input pulses are ignored while a reset is asserted. After

the reset deasserts, the first WDI falling edge is ignored for the

fast fault condition.

Figure 21. Watchdog Fast Timeout Fault

Figure 22. Watchdog Slow Timeout Fault

Figure 23. Normal Watchdog Operation

1V

0V

0V

RESET

WDI

RESET

WDI

RESET

WDI

RESET