5-511

FAST AND LS TTL DATA

SN54/74LS353

LOGIC DIAGRAM

E0b

E0a

Za

Zb

I3b

I2b

I1b

I0b

S1

I3a

I2a

I1a

I0a

14

1

2

6

7

3

4

5

9

11

12

10

13

15

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

S0

FUNCTIONAL DESCRIPTION

The SN54 / 74LS353 contains two identical 4-input Multi-

plexers with 3-state outputs. They select two bits from four

sources selected by common select inputs (S0, S1). The

4-input multiplexers have individual Output Enable (E0a, E0b)

inputs which when HIGH, forces the outputs to a high

impedance (high Z) state.

The logic equations for the outputs are shown below:

Za = E0a • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0)

Zb = E0b • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0)

If the outputs of 3-state devices are tied together, all but one

device must be in the high impedance state to avoid high

currents that would exceed the maximum ratings. Designers

should ensure that Output Enable signals to 3-state devices

whose outputs are tied together are designed so that there is

no overlap.

TRUTH TABLE

SELECT

INPUTS

DATA INPUTS

OUTPUT

OUTPUT

INPUTS

DATA INPUTS

ENABLE

OUTPUT

S0

S1

I0

I1

I2

I3

E0

Z

X

X

X

X

X

X

H

(Z)

L

L

L

X

X

X

L

H

L

L

H

X

X

X

L

L

H

L

X

L

X

X

L

H

H

L

X

H

X

X

L

L

L

H

X

X

L

X

L

H

L

H

X

X

H

X

L

L

H

H

X

X

X

L

L

H

H

H

X

X

X

H

L

L

H = HIGH Level

L = LOW Level

X = Immaterial

(Z) = High Impedance (off)

Address inputs S0 and S1 are common to both sections.